DETAILED ACTION
This office action is in response to amendment filed 7/23/2026.
Claims 1-10, 12-15, 17-20, 22 and 24 are pending. Claims 11, 16, 21, 23, and 25-42 have been canceled. Claims 1, 3-6, 8, 12-15, 17-19, and 22 have been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12-15, 17-20, 22 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner et al. US 2022/0130995 A1 (Lichtenwalner) in view of Wu et al. US 2004/0207027 A1 (Wu).
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In re claim 1, Lichtenwalner discloses (e.g. FIGs. 3-4) a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 240 (¶ 98) that comprises an active region;
a gate trench 222 (or trench defined above 232’ in FIG. 4) in an upper portion of the semiconductor layer structure 240, the gate trench having a first rounded lower corner (e.g. bottom left corner of trench 222 in FIGs. 3 and 4, or bottom left corner of trench above 232’ in FIG. 4) and a second rounded lower corner (e.g. bottom right corner of trench 222 in FIGs. 3 and 4, or bottom right corner of trench above 232’ in FIG. 4); and
a gate electrode 270 in the gate trench,
wherein the gate trench has a first rounded upper corner (upper left corner between 260 and 250) and a second rounded upper corner (upper right corner between 260 and 250), and
wherein a bottom surface of the gate trench (222 in FIG. 3 or 4, or trench above 232’ in FIG. 4) that extends between the first and second rounded lower corners has a flat portion in a cross-section view (see FIGs. 3 and 4 annotated above).
Lichtenwalner does not explicitly disclose wherein, within the active region, an upper surface of the gate electrode 270 is below or coplanar with an upper surface of the semiconductor layer structure 240.
However, Wu discloses (e.g. FIG. 5) a semiconductor device comprising a gate electrode 32 in a gate trench 44, wherein the upper surface of the gate electrode 32 is below the upper surface 42 of the semiconductor layer 12 as advantageous over an embodiment where the gate electrode 32 extends above the upper surface of the semiconductor layer, to avoid low breakdown voltage (¶ 35).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recess Lichtenwalner’s gate electrode 270 below an upper surface of the semiconductor layer structure 240 to avoid low breakdown voltage as taught by Wu.
In re claim 2, Lichtenwalner discloses (e.g. see FIGs. 3B and 4 annotated above) wherein a radius of curvature of the first rounded lower corner (lower corner at bottom of trench 222 in FIG. 3B, or lower corner of trench 222 or trench above 232’ in FIG. 4) exceeds a radius of curvature of the first rounded upper corner (upper corner between 260 and 250). See annotated FIG. 3B and FIG. 4 above showing different radii of curvature.
In re claim 3, Wu discloses (e.g. FIG. 5) wherein the upper surface of the gate electrode 32 is recessed below the upper surface 42 of the semiconductor layer 12 by at least 0.4 micrometers (¶ 36). The claimed range of at least 0.5 micros is obvious in view of Wu teaching an overlapping range. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recess the gate electrode by at least 0.5 microns to further avoid low breakdown voltage as taught by Wu.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). See MPEP 2144.05.
In re claim 4, Lichtenwalner discloses (e.g. FIGs. 3-4) wherein a sidewall of the gate trench (222 in FIG. 3 or 4, or trench above 232’ in FIG. 4) that extends from the first rounded lower corner (e.g. bottom left corner of trench 222 in FIGs. 3 and 4, or bottom left corner of trench above 232’ in FIG. 4) to the first rounded upper corner (upper left corner between 260 and 250) has a linear profile in a cross-sectional view.
In re claim 5, the combination of Lichtenwalner and Wu teaches the upper surface of the gate electrode is below the upper surface of the semiconductor layer by at least 0.4 micrometers (¶ 36 of Wu). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recess the gate electrode to below the rounded upper corners of Lichtenwalner’s gate trench to sufficiently recess the gate electrode to avoid low breakdown voltage as taught by Wu.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
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In re claim 6, Lichtenwalner discloses (e.g. FIGs. 3-4) wherein the semiconductor layer structure 240 comprises:
a drift region 220 having a first conductivity (n) type (¶ 98);
a trench shielding region (a center region of 224) having a second conductivity (p) type different from the first conductivity (n) type (¶ 98), the trench shielding region (center region of 224) extending underneath the gate trench (222 in FIGs. 3 or 4, or trench above 232’ in FIG. 4),
wherein the trench shielding region (only the center region of 224 below the flat bottom surface of the gate trench) is free of vertical overlap with the first and second rounded lower corners of the gate trench (222 in FIGs. 3 or 4, or trench above 232’ in FIG. 4).
No specific trench shielding region has been claimed that would structurally distinguish over a region of 224 (as annotated in FIGs. 3 and 4 above) that is only below the flat bottom surface of the gate trench which does not overlap the rounded lower corners.
In re claim 7, Lichtenwalner discloses (e.g. FIG. 3B and FIG. 4) wherein a radius of curvature of the first rounded lower corner (lower corner of trench 222 or trench above 232’) is at least twice a radius of curvature of the first rounded upper corner. See FIG. 3B and FIG. 4 annotated above.
In re claim 8, Lichtenwalner discloses (e.g. FIGs. 3-4) wherein the semiconductor layer structure 240 further comprises a termination region (e.g. an outer peripheral region of 240) that surrounds the active region (central region of 240), and wherein a portion of the semiconductor layer structure 240 in the active region comprises:
a drift region 220 having a first conductivity (n) type (¶ 98), wherein a portion of the drift region 220 having the first conductivity type defines the first and second rounded lower corners of the gate trench (n drift region 220 defines at least a port of the rounded lower corners of the trench 222; Lichtenwalner further discloses the p-type region 224 may not be included, ¶ 131; thus the entire trench bottom is “defined” by the n drift region 220);
a plurality of well regions 230 having a second conductivity (p) type that is different from the first conductivity (n) type on the drift region 220 (¶ 98); and
a plurality of source regions 250 having the first conductivity (n) type (¶ 98), each source region 250 in an upper portion of a respective one of the well regions 230.
In re claim 9, Lichtenwalner discloses (e.g. FIG. 3-4) further comprising:
a plurality of additional gate trenches (associated each unit cell of plurality of unit cells, ¶6,135) in the upper surface of the semiconductor layer structure 240;
a plurality of additional gate electrodes 270 (of other unit cells) in the respective plurality of additional gate trenches, where an upper surface of a portion of each additional gate electrode 270 that is within the active region is below the upper surface of the semiconductor layer structure 240 (in view of Wu as applied to claim 1 above);
a gate dielectric layer 260 in the gate trench between the gate electrode 270 and the semiconductor layer structure 240; and
a plurality of additional gate dielectric layers 260 (of other unit cells) in the respective additional gate trenches between the respective additional gate electrodes 270 and the semiconductor layer structure 240.
In re claim 10, Lichtenwalner discloses (e.g. FIGs. 3-4) further comprising a gate dielectric layer 260 in the gate trench between the gate electrode 270 and the semiconductor layer structure 240,
wherein the semiconductor device is configured so that during on-state operation a peak electric field value in the gate dielectric layer 260 will be located in a portion of the gate dielectric layer 260 that is below the upper surface of the semiconductor layer structure 240 (¶ 97,102).
No specific “on-state operation” has been claimed. Furthermore, a limitation directed to an operation state of the device does not render the device claimed structurally distinguishable over the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
In re claim 12, Lichtenwalner discloses (e.g. FIGs. 3-4) a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 240 (¶ 98) that comprises an active region;
a gate trench 222 (or trench defined above 232’ in FIG. 4) in an upper portion of the semiconductor layer structure 240, the gate trench having a first rounded lower corner (e.g. bottom left corner of trench 222 in FIGs. 3 and 4, or bottom left corner of trench above 232’ in FIG. 4), a second rounded lower corner (e.g. bottom right corner of trench 222 in FIGs. 3 and 4, or bottom right corner of trench above 232’ in FIG. 4), a first rounded upper corner (upper left corner between 260 and 250) and a second rounded upper corner (upper right corner between 260 and 250); and
a gate electrode 270 in the gate trench,
wherein a respective radius of curvature of the first rounded lower corner (lower corner at bottom of trench 222 or lower corner of trench above 232’) exceeds a respective radius of curvature of the first rounded upper corner (upper corner between 260 and 250). See annotated FIG. 3B and FIG. 4 above showing different radii of curvature.
Lichtenwalner does not explicitly disclose wherein, within the active region, an upper surface of the gate electrode 270 is below the first and second rounded upper corners of the gate trench such that the gate electrode 270 is free of horizontal overlap with the first and second rounded upper corners.
However, Wu discloses (e.g. FIG. 5) a semiconductor device comprising a gate electrode 32 in a gate trench 44, wherein the upper surface of the gate electrode 32 is below the upper surface 42 of the semiconductor layer 12 as advantageous over an embodiment where the gate electrode 32 extends above the upper surface of the semiconductor layer, to avoid low breakdown voltage (¶ 35).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recess the gate electrode to below the rounded upper corners of Lichtenwalner’s gate trench to be free of horizontal overlap to sufficiently recess the gate electrode to avoid low breakdown voltage as taught by Wu.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 13, Wu discloses (e.g. FIG. 5) wherein a first portion of the gate electrode 32 is within the active region and a second portion of the gate electrode 32 is outside the active region (connection to gate electrode made locally at one or more other locations on the die which are not shown, ¶ 35), and wherein an upper surface of the first portion of the gate electrode 32 (see FIG. 5) is below an upper surface 42 of the semiconductor layer structure 12.
In re claim 14, Wu discloses (e.g. FIG. 5) wherein the upper surface of the gate electrode 32 is recessed below an upper surface 42 of the semiconductor layer 12 by at least 0.4 micrometers (¶ 36). The claimed range of at least 0.5 micros is obvious in view of Wu teaching an overlapping range. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recess the gate electrode by at least 0.5 microns to further avoid low breakdown voltage as taught by Wu.
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997). See MPEP 2144.05.
In re claim 15, Lichtenwalner discloses (e.g. FIGs. 3-4) wherein a sidewall of the gate trench (222 in FIG. 3 or 4, or trench above 232’ in FIG. 4) that extends from the first rounded lower corner (e.g. bottom left corner of trench 222 in FIGs. 3 and 4, or bottom left corner of trench above 232’ in FIG. 4) to the first rounded upper corner (upper left corner between 260 and 250) has a linear profile in a cross-sectional view.
In re claim 17, Lichtenwalner discloses (e.g. FIGs. 3-4) further comprising a gate dielectric layer 260 in the gate trench between the gate electrode 270 and the semiconductor layer structure 240,
wherein the semiconductor device is configured so that during on-state operation a peak electric field value in the gate dielectric layer 260 will be located in a portion of the gate dielectric layer 260 that is below an upper surface of the semiconductor layer structure 240 (¶ 97,102).
No specific “on-state operation” has been claimed. Furthermore, a limitation directed to an operation state of the device does not render the device claimed structurally distinguishable over the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
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In re claim 18, Lichtenwalner discloses (e.g. FIG. 4) a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 240 (¶ 98) that comprises an active region;
a gate trench 222 (or trench defined above 232’) in an upper portion of the semiconductor layer structure 240, the gate trench having a first rounded lower corner (e.g. bottom left corner of trench 222 or bottom left corner of trench above 232’) and a second rounded lower corner (e.g. bottom right corner of trench 222 or bottom right corner of trench above 232’);
a gate electrode 270 in the gate trench,
a gate dielectric layer 260 in the gate trench between the gate electrode 270 and the semiconductor layer structure 240,
wherein a portion of the gate dielectric layer 260 that is on a bottom surface of the gate trench between the first and second rounded lower corners comprises an upper surface with a flat profile in a cross-sectional view, and
wherein the semiconductor device is configured so that a peak electric field in the gate dielectric layer 260 during on-state operation is below an upper surface of the semiconductor layer structure 240 (¶ 97,102).
No specific “on-state operation” has been claimed. Furthermore, a limitation directed to an operation state of the device does not render the device claimed structurally distinguishable over the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
Lichtenwalner does not explicitly disclose wherein, within the active region, an upper surface of the gate electrode 270 is below or coplanar with an upper surface of the semiconductor layer structure 240.
However, Wu discloses (e.g. FIG. 5) a semiconductor device comprising a gate electrode 32 in a gate trench 44, wherein the upper surface of the gate electrode 32 is below the upper surface 42 of the semiconductor layer 12 as advantageous over an embodiment where the gate electrode 32 extends above the upper surface of the semiconductor layer, to avoid low breakdown voltage (¶ 35).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recess Lichtenwalner’s gate electrode 270 below an upper surface of the semiconductor layer structure 240 to avoid low breakdown voltage as taught by Wu.
In re claim 19, Wu discloses (e.g. FIG. 5) wherein the upper surface of the gate electrode 32 is below the upper surface 42 of the semiconductor layer structure 12.
Lichtenwalner discloses (e.g. FIG. 4) wherein the semiconductor layer structure 240 comprises:
a drift region 220 having a first conductivity (n) type (¶ 98);
a trench shielding region (a center region of 224) having a second conductivity (p) type different from the first conductivity (n) type (¶ 98), the trench shielding region (center region of 224) extending underneath the gate trench (222 or trench above 232’ in FIG. 4),
wherein the trench shielding region (only the center region of 224 below the flat bottom surface of the gate trench) is free of vertical overlap with the first and second rounded lower corners of the gate trench (222 or trench above 232’ in FIG. 4).
No specific trench shielding region has been claimed that would structurally distinguish over a region of 224 (as annotated in FIG. 4 above) that is only below the flat bottom surface of the gate trench which does not overlap the rounded lower corners.
In re claim 20, Lichtenwalner discloses (e.g. FIG. 4) wherein the gate trench further has a first rounded upper corner (upper left corner between 260 and 250) and a second rounded upper corner (upper right corner between 260 and 250), and wherein a radius of curvature of the first rounded lower corner (lower corner at bottom of trench 222 or lower corner of trench above 232’) exceeds a radius of curvature of the second rounded upper corner (upper corner between 260 and 250). See annotated FIG. 4 above showing different radii of curvature.
In re claim 22, Lichtenwalner discloses (e.g. FIG. 4) wherein the gate trench further has a first rounded upper corner (upper left corner between 260 and 250) and a second rounded upper corner (upper right corner between 260 and 250).
Lichtenwalner does not explicitly disclose wherein, within the active region, the upper surface of the gate electrode 270 is below the first and second rounded upper corners of the gate trench such that the gate electrode 270 is free of horizontal overlap with the first and second rounded upper corners.
However, Wu discloses (e.g. FIG. 5) a semiconductor device comprising a gate electrode 32 in a gate trench 44, wherein the upper surface of the gate electrode 32 is below the upper surface 42 of the semiconductor layer 12 as advantageous over an embodiment where the gate electrode 32 extends above the upper surface of the semiconductor layer, to avoid low breakdown voltage (¶ 35).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recess the gate electrode to below the rounded upper corners of Lichtenwalner’s gate trench to be free of horizontal overlap to sufficiently recess the gate electrode to avoid low breakdown voltage as taught by Wu.
“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 24, Lichtenwalner discloses (e.g. FIG. 4) wherein the gate trench further has a first rounded upper corner (upper corner between 260 and 250), and wherein a radius of curvature of the first rounded lower corner (lower corner of trench 222 or trench above 232’) is at least twice a radius of curvature of the first rounded upper corner. See FIG. 4 annotated above.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10, 12-15, 17-20, 22 and 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
