Prosecution Insights
Last updated: April 19, 2026
Application No. 18/453,422

SEMICONDUCTOR PACKAGE

Non-Final OA §102§103
Filed
Aug 22, 2023
Examiner
HOSSAIN, MOAZZAM
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
98%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
694 granted / 792 resolved
+19.6% vs TC avg
Moderate +11% lift
Without
With
+10.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
52 currently pending
Career history
844
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
45.5%
+5.5% vs TC avg
§102
31.3%
-8.7% vs TC avg
§112
16.6%
-23.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 792 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election of Species I in the “Response to Election / Restriction Filed - 12/18/2025”, is acknowledged. However, Applicant’s selection of claims 1-17 readable on species I, seems not accurate. At least, claims 10 and 15 are not readable on Species II, because “a post” recited thereon is disclosed in Figure 3A and paragraph [0061] which were identified as part of ‘Species II’ in “Requirement for Restriction/Election - 10/22/2025”. Additionally, applicant did not distinctly indicate whether election was provisional or “without traverse”. As applicant had not provided any reason for “provisional election” or any errors in the restriction requirement, the election for the species I is considered “without traverse” and is made final. In view of the above, this office action considers claims 1-20 pending for prosecution, of which, non-elected claims 10, 15 and 18-20 are considered as withdrawn, and elected claims 1-9, 11-14 and 16-17 are examined on their merits. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as 6; Fig 1; [0050]) = (element 6; Figure No. 1; Paragraph No. [0050]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claim 11 and 16-17 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by HUANG; Wen Hung et al. (US 20190348352 A1) hereinafter Huang. Regarding claim 11. Huang teaches a semiconductor package (package [0043]), comprising (see the entire document; Figs 1-2 along with Figs 3-28; specifically, and as cited below): PNG media_image1.png 480 1537 media_image1.png Greyscale Huang Figures 1 and Figure 2 a redistribution substrate (comprising {2 to 5}; Fig 1; [0050]) including an insulating layer (one or more from {10, 20, 30, 40}) and a first redistribution pattern (23 [0052]), and a connection conductive pattern (21, 22 comprising {211,222, 24, 25,254 26); a semiconductor chip (6; Fig 1; [0050]) electrically connected to the redistribution substrate (comprising {2 to 5}); and a solder ball (14; [0050, 0072]) in contact with the connection conductive pattern (21,22), wherein the connection conductive pattern (21, 22 comprising {211,222, 24, 25, 26) comprises: an under-bump (labelled as ball pad 25, filled in the opening 104; Figs 1-2; [0051-0052]; where filled layer 25, in opening 104, is made of copper [0047]) including an upper portion (25 over 24 in 22b region) and a lower portion (254) having a width smaller (because no 24) than the upper portion; and a first barrier layer (24) and a second barrier layer (26), wherein each of the first barrier layer (24) and the second (26) barrier layer surrounds the lower portion (254) of the under-bump (25) in a plan view, wherein the solder ball (14) is in contact (since no 24) with a bottom surface of the lower portion of the under-bump (254). Regarding claim 16. Huang as applied to the semiconductor package of claim 11, further teaches, wherein the redistribution pattern (RDL 23 along with 22) comprises: a first redistribution barrier layer (24; Figs 1-2; [0055]); a second redistribution barrier layer (26) on the first redistribution barrier layer; and a via structure (labelled as ball pad 25, filled in the opening 104; Figs 1-2; [0051-0052]; via is construed from filled layer of 25 made of copper [0047], in opening 104 or in recess 22a [0058] ) on the second redistribution barrier layer (26). Regarding claim 17. Huang as applied to the semiconductor package of claim 16, further teaches, (the package) further comprising a connection structure (5; Fig 1; [0050]) connecting the semiconductor chip (6) to the redistribution substrate (comprising {2 to 5}; Fig 1; [0050]), wherein the connection structure (5) is in contact (through conducting structure 3 and 4) with the first redistribution barrier layer (24), the second redistribution barrier layer (26), and the via structure (labelled as ball pad 25, filled in the opening 104; Figs 1-2; [0051-0052] via is construed from filled layer of 25 made of copper [0047], in opening 104 or in recess 22a [0058] ). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-9 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over HUANG; Wen Hung et al. (US 20190348352 A1) hereinafter Huang in view of Theil; Jeremy Alfred et al., (US 20230197655 A1); hereinafter Theil. Regarding claim 1. Huang teaches a semiconductor package (package [0043]), comprising (see the entire document; Figs 1-3 along with Figs 4-28; specifically, and as cited below): a redistribution substrate (comprising {2 to 5}; Fig 1; [0050]) including an insulating layer (one or more from {10, 20, 30, 40}) and a first redistribution pattern (23 with 22; [0052]); and a semiconductor chip (6; Fig 1A; [0050]) electrically connected to the redistribution substrate (comprising {2 to 5}), wherein the first redistribution pattern (RDL 23 along with 22) comprises (Fig 1; [0055]): a first barrier layer (24); a second barrier layer (26; [0064]) on the first barrier layer; and a via structure (labelled as ball pad 25, filled in the opening 104; Figs 1-2; [0051-0052]; via is construed from filled layer of 25 made of copper [0047], in opening 104 or in recess 22a [0058] ) on the second barrier layer (26), wherein the first barrier layer (24) comprises a first conductive material (nickel) and the second barrier layer (26) comprises a second conductive material (nickel). (see below different from the first conductive material). The difference between Huang and claimed subject matter is first and second conductive material (of barrier layers) are different. However, in the analogous art, Theil teaches (Fig 7A-7G; [0166]) a redistribution layer or RDL 940 having barrier layers 942,946 and a via 948, wherein [ 0079] wherein the first and the second conductive barrier layers comprise a material selected from the group consisting of, inter alia, titanium (Ti), titanium nitride (TiN), Nickel (Ni), Nickel-Vanadium (NiV), and combinations thereof. In effect Theil recognizes that Nickel is equivalent to titanium (Ti), titanium nitride (TiN) and are functionally equivalent as barrier conductors. According to MPEP § 2144.06.II, "In order to rely on equivalence as a rationale supporting an obviousness rejection, the equivalency must be recognized in the prior art" In re Ruff, 256 F.2d 590, 118 USPQ 340 (CCPA 1958). Therefore, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to substitute Huang’s functionally equivalent Nickel of barrier layers 24, 26 by other functionally equivalent materials i.e. the first conductive material (of 24) comprises titanium nitride (TiN) and the second conductive material (of 26) comprises titanium (Ti) as taught by Thiel. Thus, inter alia, the limitation “a ferromagnetic liquid with iron powder” is not patentable over the combination of (Huang and Theil). It has been held that the substitution of one prior teaching by another art supports an obviousness rejection, as in the instant case, the equivalency is being recognized in the prior art, and the substitution is then within the level of ordinary skill in the art. [MPEP 2144.06.II]. Regarding claim 2. the combination of (Huang and Theil) as applied to the semiconductor package of claim 1, further teaches, wherein the first conductive material (of 24) comprises titanium nitride (TiN) (in view of Theil). Regarding claim 3. the combination of (Huang and Theil) as applied to the semiconductor package of claim 1, further teaches, wherein the second conductive material (of 26) comprises titanium (Ti) (in view of Theil). Regarding claim 4. the combination of (Huang and Theil) as applied to the semiconductor package of claim 1, further teaches, wherein the first barrier layer has a thickness in a range from 1 nm to 30 nm (obvious from Theil [0135] 10nm). Regarding claim 5. the combination of (Huang and Theil) as applied to the semiconductor package of claim 1, further teaches, wherein the second barrier layer has a thickness in a range from 1 nm to 500 nm (obvious from Theil [0135] 400 nm). Regarding claim 6. the combination of (Huang and Theil) as applied to the semiconductor package of claim 1, further teaches, wherein a thickness of the first barrier layer (obvious from Theil [0135] 10nm) is smaller (obvious from Theil) than a thickness of the second barrier layer (obvious from Theil [0135] 4000nm). Regarding claim 7. the combination of (Huang and Theil) as applied to the semiconductor package of claim 1, further teaches, (the package) further comprising a connection structure (5; Fig 1; [0050]) connecting the semiconductor chip (6) to the redistribution substrate (comprising {2 to 5}; Fig 1; [0050]) and a mold layer (16) surrounding the semiconductor chip (6) in a plan view, wherein the first barrier layer (24) , the second barrier layer (26) , and the via structure (labelled as ball pad 25, filled in the opening 104; Figs 1-2; [0051-0052] via is construed from filled layer of 25 made of copper [0047], in opening 104 or in recess 22a [0058]) are in contact with the connection structure (5; through conducting structure 3 and 4), and the mold layer (16) is spaced apart ( fig 1) from the first barrier layer (24) and the second barrier layer (26). Regarding claim 8. the combination of (Huang and Theil) as applied to the semiconductor package of claim 1, further teaches, wherein the redistribution substrate (comprising {2 to 5}; Fig 1; [0050]) further comprises a second redistribution pattern (32; [0064]) connected to the first redistribution pattern (23), and the second redistribution pattern (32) comprises a via structure (404; [0065]) in contact with a bottom surface of the first barrier layer (24) of the first redistribution pattern (23). Regarding claim 9. the combination of (Huang and Theil) as applied to the semiconductor package of claim 1, further teaches, wherein the via structure (labelled as ball pad 25, filled in the opening 104; Figs 1-2; [0051-0052]; via is construed from filled layer of 25 made of copper [0047], in opening 104 or in recess 22a [0058] ) comprises copper (Cu) ([0047]). Regarding claim 12. Huang as applied to the semiconductor package of claim 11, does not expressly disclose, wherein the first barrier layer (24) comprises titanium nitride (TiN), and the second barrier layer (26) comprises titanium (Ti), Huang discloses those Nickel.. This the difference between Huang and claimed subject matter is first and second conductive material (of barrier layers) are different. However, in the analogous art as used in claim 1 rejection, Theil teaches (Fig 7A-7G; [0166]) a redistribution layer or RDL 940 having barrier layers 942,946 and a via 948, wherein [ 0079] wherein the first and the second conductive barrier layers comprise a material selected from the group consisting of, inter alia, titanium (Ti), titanium nitride (TiN), Nickel (Ni), Nickel-Vanadium (NiV), and combinations thereof. In effect Theil recognizes that Nickel is equivalent to titanium (Ti), titanium nitride (TiN) and are functionally equivalent as barrier conductors. According to MPEP § 2144.06.II, "In order to rely on equivalence as a rationale supporting an obviousness rejection, the equivalency must be recognized in the prior art" In re Ruff, 256 F.2d 590, 118 USPQ 340 (CCPA 1958). Therefore, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to substitute Huang’s functionally equivalent Nickel of barrier layers 24, 26 by other functionally equivalent materials i.e. the first conductive material (of 24) comprises titanium nitride (TiN) and the second conductive material (of 26) comprises titanium (Ti) as taught by Thiel. Thus, inter alia, the limitation “a ferromagnetic liquid with iron powder” is not patentable over the combination of (Huang and Theil). It has been held that the substitution of one prior teaching by another art supports an obviousness rejection, as in the instant case, the equivalency is being recognized in the prior art, and the substitution is then within the level of ordinary skill in the art. [MPEP 2144.06.II]. Regarding claim 13. the combination of (Huang and Theil) as applied to the semiconductor package of claim 12, wherein the under-bump (labelled as ball pad 25, filled in the opening 104; Figs 1-2; [0051-0052]; where filled layer 25, in opening 104, is made of copper [0047]) comprises copper (Cu). Regarding claim 14. Huang as applied to the semiconductor package of claim 11, does not expressly disclose, wherein the first barrier layer (24) has a thickness in a range from 1 nm to 30 nm, and the second barrier layer has (26) a thickness in a range from 1 nm to 500 nm. However, from rejection analysis claim 1, 12 rejection, above, it is established as obvious that the combination of (Huang and Theil) discloses first conductive material (of 24) comprises titanium nitride (TiN) and the second conductive material (of 26) comprises titanium (Ti) as taught by Thiel. Thiel further teaches the first barrier layer (24) has a thickness in a range from 1 nm to 30 nm, obvious from Theil [0135] 10nm) and the second barrier layer has a thickness in a range from 1 nm to 500 nm (obvious from Theil [0135] 400 nm). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898 February 26, 2026
Read full office action

Prosecution Timeline

Aug 22, 2023
Application Filed
Feb 26, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
98%
With Interview (+10.7%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 792 resolved cases by this examiner. Grant probability derived from career allow rate.

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