Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Integrated circuit device including via power rail extends through device isolation film”.
Abstract
The abstract of the disclosure is objected to because it is written in legal terminology which is too similar to claim language. In particular, legal phraseology such as the term “comprising” and “wherein” which are commonly used to define the limitations and scope pf patent claims, should generally be avoided in U.S. patent abstracts because the purpose of the abstract is not to define the patent claims, but to provide the reader with a clear and concise summary. The abstract should use plain language to describe the invention's technical problem, solution, and principal use. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” etc. Correction is required. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 20210375722).
Regarding claim 1. Fig 1 and Fig 2 (a lateral portion view of Fig 1) of Kim disclose An integrated circuit device comprising:
a substrate 101/102 ([0023]: ‘substrate 101 having 102’);
a fin-type active region 105 [0023] that extends from the substrate to define a portion of a trench region (the trench region where 162b is located) on the substrate (Fig 2),
wherein the fin-type active region extends in a first lateral direction (Fig 1: X);
a device isolation film 162 [0030] on the trench region (Fig 2);
an insulating liner structure 131/251 [0034]/[0035] that extends through the substrate in a vertical direction (Fig 2),
wherein the insulating liner structure contacts the device isolation film at a first vertical level (Fig 2: refer to 131, the vertical level that is colinear to the top surface of 102);
a via power rail 120 that extends through the device isolation film in the vertical direction,
wherein the via power rail comprises a first bottom surface (the bottom surface of 120) at a second vertical level (the vertical level below top surface of 102),
wherein a distance of the second vertical level from a surface (the top surface of 102) of the substrate is greater than a distance of the first vertical level from the surface of the substrate (Fig 2: because the bottom surface of 120 is deeper than the bottom surface of 131 in the substrate); and
a backside power rail 255/M2 comprising a main rail 255 and a protrusion rail (M2),
wherein the main rail extends through the substrate and the insulating liner structure in the vertical direction (Fig 2), and
wherein the protrusion rail is connected to the main rail, extends from the main rail toward the via power rail (Fig 2), and is between the device isolation film in a second lateral direction (Fig 1: Y) that intersects the first lateral direction (Fig 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 8, 10-13, 15-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20210375722) in view of in view of Su (US 20220384602).
Regarding claim 3. Kim discloses The integrated circuit device of claim 1 except further comprising a via insulating spacer that extends through the device isolation film in the vertical direction, wherein the via insulating spacer at least partially surrounds a sidewall of the backside power rail,
wherein the insulating liner structure comprises a first insulating liner and a second insulating liner, wherein the first insulating liner contacts the device isolation film at the first vertical level, wherein the first insulating liner is between the second insulating liner and the device isolation film,
wherein the first insulating liner and the second insulating liner comprise different materials from each other, and
wherein the via insulating spacer and the first insulating liner comprise a same material as each other.
However, Su discloses a via insulating spacer 390 [0082] that extends through the device isolation film 160 [0082] in the vertical direction (Fig 35C),
wherein the via insulating spacer at least partially surrounds a sidewall of the backside power rail 152/402 (380 surrounds a sidewall of the 152),
wherein the insulating liner structure comprises a first insulating liner 140 [0028] and a second insulating liner 380 [0082],
wherein the first insulating liner contacts the device isolation film at the first vertical level (Fig 35C),
wherein the first insulating liner is between the second insulating liner and the device isolation film (Fig 35C),
wherein the first insulating liner and the second insulating liner comprise different materials from each other ([0028]/[0082]: 140 is low-k material SiO2 but 380 is high-k material HfO2), and
wherein the via insulating spacer and the first insulating liner comprise a same material as each other ([0082]: 390 is also low-k material SiO2).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kim’s device structure to have the Su’s structure for the purpose of providing enhanced device performance and efficiency due to a more optimized power delivery network that separates power and signal lines, leading to reduced resistance and voltage drop, less power noise, and increased transistor density because the front side of the chip is freed up for signal routing.
Regarding claim 8. Kim discloses The integrated circuit device of claim 1, further comprising:
a source/drain region 110 on the fin-type active region (Fig 2);
a gate line (GS) that extends in the second lateral direction and on the fin-type active region (Fig 1/Fig 2).
But Kim does disclose a nanosheet stack between the fin-type active region and the gate line,
wherein the nanosheet stack comprises at least one nanosheet,
wherein the gate line at least partially surrounds the at least one nanosheet, and wherein the at least one nanosheet contacts the source/drain region,
wherein the backside power rail is spaced apart from the source/drain region and the nanosheet stack in the second lateral direction and extends through the gate line in the vertical direction.
However, Su discloses a nanosheet stack 124 [0020] between the fin-type active region and the gate line (Fig 35B), wherein the nanosheet stack comprises at least one nanosheet (Fig 35B),
wherein the gate line 290 at least partially surrounds the at least one nanosheet, and wherein the at least one nanosheet contacts the source/drain region (Fig 35B),
wherein the backside power rail 152/402 is spaced apart from the source/drain region and the nanosheet stack in the second lateral direction and extends through the gate line in the vertical direction (Fig 35B).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kim’s device structure to have the Su’s structure for the purpose of providing enhanced performance and power efficiency due to enhanced gate control with nanosheet based channel structure, which alleviates short-channel effects.
Regarding claim 10. Kim discloses The integrated circuit device of claim 1 except further comprising a via insulating spacer that extends through the device isolation film in the vertical direction,
wherein the via insulating spacer at least partially surrounds a sidewall of the backside power rail,
wherein the insulating liner structure comprises a first insulating liner and a second insulating liner,
wherein the first insulating liner contacts the device isolation film at the first vertical level, and
wherein the first insulating liner is between the second insulating liner being and the device isolation film,
the via insulating spacer and the first insulating liner comprise a material selected from silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN), and
the second insulating liner comprises a material selected from silicon oxide (SiO), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN).
However, Su discloses a via insulating spacer 390 [0082] that extends through the device isolation film 160 [0082] in the vertical direction (Fig 35C),
wherein the via insulating spacer at least partially surrounds a sidewall of the backside power rail 152/402 (380 surrounds a sidewall of the 152),
wherein the insulating liner structure comprises a first insulating liner 140 [0028] and a second insulating liner 380 [0082],
wherein the first insulating liner contacts the device isolation film at the first vertical level (Fig 35C), and
wherein the first insulating liner is between the second insulating liner being and the device isolation film (Fig 35C),
the via insulating spacer and the first insulating liner comprise a material selected from silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN) [0028], and
the second insulating liner comprises a material selected from silicon oxide (SiO), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN) [0082].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kim’s device structure to have the Su’s structure for the purpose of providing enhanced device performance and efficiency due to a more optimized power delivery network that separates power and signal lines, leading to reduced resistance and voltage drop, less power noise, and increased transistor density because the front side of the chip is freed up for signal routing.
Regarding claim 11. Fig 1 and Fig 2 (a lateral portion view of Fig 1) of Kim disclose An integrated circuit device comprising:
a substrate 101/102 ([0023]: ‘substrate 101 having 102’);
a pair of fin-type active regions 105 (the 105 in left side of 120 and the 105 in right side of 120, thus being a pair) that extend from the substrate in a first lateral direction to define a plurality of trench regions (the trench region where 162b is located) on the substrate;
a pair of source/drain regions 110 arranged one-by-one on the pair of fin-type active regions, respectively (Fig 2);
a device isolation film 162b on the trench region;
an insulating liner structure 131/251 [0034]/[0035] that extends through the substrate in a vertical direction (Fig 2),
wherein the insulating liner structure contacts the device isolation film at a first vertical level (Fig 2: refer to 131, the vertical level that is colinear to the top surface of 102);
a via power rail 120 between the pair of fin-type active regions and between the pair of source/drain regions (Fig 2),
wherein the via power rail extends through the device isolation film in the vertical direction (Fig 2),
wherein the via power rail comprises a first bottom surface (the bottom surface of 120) at a second vertical level (the vertical level below top surface of 102),
wherein a distance of the second vertical level from a surface (the top surface of 102) of the substrate is greater than a distance of the first vertical level from the surface of the substrate (Fig 2: because the bottom surface of 120 is deeper than the bottom surface of 131 in the substrate);
a backside power rail 255/M2; and
wherein the backside power rail comprises a main rail 255 and a protrusion rail (M2),
wherein the main rail extends through the substrate and the insulating liner structure in the vertical direction (Fig 2), and
wherein the protrusion rail is connected to the main rail, extends from the main rail toward the via power rail (Fig 2).
But Kim does not disclose a via insulating spacer that extends through the device isolation film in the vertical direction,
wherein the via insulating spacer at least partially surrounds a sidewall of the backside power rail, the protrusion rail is connected to the main rail extends from the main rail toward the via power rail the via insulating spacer, and is between the device isolation film in a second lateral direction that intersects the first lateral direction.
However, Su discloses a via insulating spacer 380 [0082] that extends through the device isolation film 160 [0082] in the vertical direction,
wherein the via insulating spacer at least partially surrounds a sidewall of the backside power rail 152/402 (380 surrounds a sidewall of the 152), the protrusion rail 402 is connected to the main rail 152 extends from the main rail toward the via power rail the via insulating spacer, and is between the device isolation film in a second lateral direction that intersects the first lateral direction (Fig 35C).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kim’s device structure to have the Su’s structure for the purpose of providing enhanced device performance and efficiency due to a more optimized power delivery network that separates power and signal lines, leading to reduced resistance and voltage drop, less power noise, and increased transistor density because the front side of the chip is freed up for signal routing.
Regarding claim 12. Kim in view of Su discloses The integrated circuit device of claim 11. But Kim in view of Su does not explicitly disclose a length of the via insulating spacer in the vertical direction is greater than a length of the via power rail in the vertical direction.
However, the difference between the claimed limitation and Kim in view of Su’s device is the length dimension of the via insulating spacer and the via power rail in the vertical direction. Although the Kim in view of Su’s device does not teach the exact distance of the support means as that claimed by Applicant, the length differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes.
Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the support means is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of providing support. In re Dailey, 149 USPQ 47 (CCPA 1976). It appears that these changes produce no functional differences and therefore would have been obvious.
Regarding claim 13. Kim in view of Su discloses The integrated circuit device of claim 11. But Kim in view of Su does not explicitly disclose wherein a length of the via insulating spacer in the vertical direction is less than a length of the via power rail in the vertical direction.
However, the difference between the claimed limitation and Kim in view of Su’s device is the length dimension of the via insulating spacer and the via power rail in the vertical direction. Although the Kim in view of Su’s device does not teach the exact distance of the support means as that claimed by Applicant, the length differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes.
Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the support means is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of providing support. In re Dailey, 149 USPQ 47 (CCPA 1976). It appears that these changes produce no functional differences and therefore would have been obvious.
Regarding claim 15. Kim in view of Su discloses The integrated circuit device of claim 11, Su discloses wherein the via insulating spacer has a second bottom surface, and the protrusion rail contacts the first bottom surface of the via power rail and the second bottom surface of the via insulating spacer (Fig 35C).
Regarding claim 16. Kim in view of Su discloses The integrated circuit device of claim 11, Su discloses wherein the insulating liner structure comprises a first insulating liner 140 [0028] and a second insulating liner 380 [0082],
wherein the first insulating liner contacts the device isolation film at the first vertical level (Fig 35C),
wherein the first insulating liner is between the second insulating liner and the device isolation film (Fig 35C),
the first insulating liner and the second insulating liner comprise different materials from each other ([0028]/[0082]: 140 is low-k material SiO2 but 380 is high-k material HfO2), and
the via insulating spacer 390 and the first insulating liner comprise a same material as each other ([0082]: 390 is also low-k material SiO2).
Regarding claim 18. Kim in view of Su discloses The integrated circuit device of claim 11, Su discloses wherein the insulating liner structure comprises a first insulating liner 140 and a second insulating liner 380,
wherein the first insulating liner contacts the device isolation film at the first vertical level (Fig 35C),
wherein the first insulating liner is between the second insulating liner and the device isolation film (Fig 35C), and
the backside power rail further comprises a horizontal extension that extends from the main rail in the second lateral direction (Fig 35C: the laterally extend portion of 402),
wherein the horizontal extension is between a portion of the device isolation film and the second insulating liner (Fig 35C).
Regarding claim 19. Fig 1 and Fig 2 (a lateral portion view of Fig 1) of Kim disclose An integrated circuit device comprising:
a substrate 101/102 ([0023]: ‘substrate 101 having 102’);
a fin-type active region 105 that extends from the substrate to define a trench region (the trench region where 162b is located) on the substrate (Fig 2);
wherein the gate line (GS) extends in a lateral direction (Fig 1);
a source/drain region 110 adjacent to the gate line (GS),
a device isolation film 162 [0030] on a sidewall of the fin-type active region and on the trench region (Fig 2);
an insulating liner structure 131/251 [0034]/[0035] that extends through the substrate in a vertical direction (Fig 2),
a via power rail 120 spaced apart from each of the fin-type active region, the source/drain region, and the gate line in the lateral direction (Fig 2),
wherein the via power rail extends through the device isolation film in the vertical direction and comprises a first bottom surface (the bottom surface of 120) at a second vertical level (the vertical level below top surface of 102),
wherein a distance of the second vertical level from a surface of the substrate is greater than a distance of the first vertical level (Fig 2: refer to 131, the vertical level that is colinear to the top surface of 102) from the surface of the substrate (Fig 2: because the bottom surface of 120 is deeper than the bottom surface of 131 in the substrate);
a backside power rail 255/M2,
wherein the backside power rail comprises a main rail 255 and a protrusion rail (M2),
wherein the main rail extends through the substrate and the insulating liner structure in the vertical direction (Fig 2), and
wherein the protrusion rail is connected to the main rail (Fig 2), extends from the main rail toward the via power rail and is between the device isolation film in the lateral direction (Fig 2),
But Kim does not disclose at least one nanosheet on the fin-type active region,
wherein the at least one nanosheet is spaced apart from a fin top surface of the fin-type active region;
a gate line that at least partially surrounds the at least one nanosheet on the fin-type active region,
wherein the source/drain region contacts the at least one nanosheet;
wherein the insulating liner structure comprises a first insulating liner and a second insulating liner, wherein the first insulating liner contacts the device isolation film at a first vertical level, and wherein the first insulating liner is between the second insulating liner and the device isolation film;
a via insulating spacer that extends through the device isolation film in the vertical direction,
wherein the via insulating spacer at least partially surrounds a sidewall of the backside power rail, and
wherein the protrusion rail toward the via insulating spacer.
However, Su discloses at least one nanosheet 124 [0020] on the fin-type active region (Fig 35B), wherein the at least one nanosheet is spaced apart from a fin top surface of the fin-type active region (Fig 35B);
a gate line 290 that at least partially surrounds the at least one nanosheet on the fin-type active region (Fig 35B),
wherein the source/drain region 250S contacts the at least one nanosheet (Fig 35A);
wherein the insulating liner structure comprises a first insulating liner 140/404 [0028]/[0083] and a second insulating liner 380 [0082] (Fig 35C), wherein the first insulating liner contacts the device isolation film 160 at a first vertical level (Fig 35C), wherein the first insulating liner is between the second insulating liner and the device isolation film (Fig 35C);
a via insulating spacer 390 [0082] that extends through the device isolation film in the vertical direction (Fig 35C),
wherein the via insulating spacer at least partially surrounds a sidewall of the backside power rail (Fig 35C),
wherein the protrusion rail 402 extends from the main rail 152 toward the via power rail and the via insulating spacer (Fig 35C).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Kim’s device structure to have the Su’s structure for the purpose of providing enhanced device performance and efficiency due to a more optimized power delivery network that separates power and signal lines, leading to reduced resistance and voltage drop, less power noise, and increased transistor density because the front side of the chip is freed up for signal routing.
Regarding claim 20. Kim in view of Su discloses The integrated circuit device of claim 19, Su discloses wherein the backside power rail comprises a first surface (any surface of ‘backside power rail’ contacts its own ‘backside power rail’) that contacts the backside power rail, a second surface that contacts the insulating liner structure (Fig 35C), a third surface that contacts the via insulating spacer, and a fourth surface that contacts the device isolation film (Fig 35C),
the via insulating spacer and the first insulating liner comprise a material selected from silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN) [0082], and
the second insulating liner is selected from silicon oxide (SiO), silicon oxynitride (SiON), and silicon oxycarbonitride (SiOCN) [0082].
Allowable Subject Matter
Claims 2, 4-7, 9, 14 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the protrusion rail contacts the first bottom surface of the backside power rail and the second bottom surface of the via insulating spacer”.
Regarding claim 4. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the protrusion rail of the backside power rail comprises a curved surface and contacts the second bottom surface of the via insulating spacer”.
Regarding claim 5. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the via insulating spacer comprises a second bottom surface at a third vertical level, a distance of the third vertical level from the surface of the substrate is greater than the distance of the second vertical level from the surface of the substrate, and the backside power rail contacts the first bottom surface of the backside power rail, the sidewall of the backside power rail, and the second bottom surface of the via insulating spacer”.
Regarding claim 6. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the backside power rail further comprises a vertical extension that extends from the protrusion rail toward the via insulating spacer in the vertical direction, and the vertical extension is between the sidewall of the via power rail and at least a portion of the device isolation film”.
Regarding claim 7. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the backside power rail further comprises a vertical extension and a horizontal extension, the vertical extension extends from the protrusion rail toward the via insulating spacer in the vertical direction and is between the sidewall of the via power rail and a portion of the device isolation film, and the horizontal extension extends from the main rail in the second lateral direction and is between the portion of the device isolation film and the second insulating liner”.
Regarding claim 9. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a distance between the pair of inner sidewalls in the second lateral direction gradually increases toward the surface of the substrate”.
Regarding claim 14. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the via insulating spacer has a second bottom surface at a third vertical level, a distance of the third vertical level from the surface of the substrate is greater than a distance of the second vertical level from the surface of the substrate”.
Regarding claim 17. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the backside power rail further comprises a vertical extension that extends from the protrusion rail toward the via insulating spacer in the vertical direction, the vertical extension is between the sidewall of the via power rail and a portion of the device isolation film”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812