DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-11, and 13-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20240047451 (Yan et al).
Concerning claim 1, Yan discloses a III-nitride semiconductor based heterojunction integrated circuit (IC), comprising (Figs. 1, 2, and 10A-10F):
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a substrate (102) ([0023]); a III-nitride semiconductor region located over the substrate, wherein the III- nitride semiconductor region (circular enclosed region in annotated Fig. 2 above) comprises a heterojunction comprising at least one two- dimensional carrier gas of a second conductivity type (Fig. 2, [0022], [0027], and [0069]); a power device comprising: a first terminal (D) operatively connected to the III-nitride semiconductor region; a second terminal (S) operatively connected to the Ill-nitride semiconductor region and laterally spaced from the first terminal (Fig. 2); a gate structure (G) located above the III-nitride semiconductor region and laterally spaced between the first and second terminals; and a control gate terminal (110) operatively connected to the gate structure, wherein the control gate terminal is configured such that a potential applied to the control gate terminal modulates and controls a current flow through the two- dimensional carrier gas between the first and second terminals ([0030] and [0070], note that the gate structure is formed such that a p-GaN layer is formed directly on the barrier layer 106 and then a metal gate layer (control gate) is formed over the p-GaN gate layer); a second device (rectangular enclosed region in the annotated Fig. 2 above) comprising at least one second two-dimensional carrier gas of the second conductivity type ([0022], [0027], and [0069]); an isolation region (162) between the power device and the second device such that the two dimensional carrier gas of the power device and the second two dimensional carrier gas of the second device are separated by the isolation region to form two distinctive active areas of two dimensional carrier gas (Fig. 2 and [0046]-[0049]); and at least one region of a first conductivity type positioned laterally between an active area of the power device and an active area of the second device ([0046]-[0049], note that the one region of first conductivity type is also the isolation region), wherein a Schottky or ohmic metal contact (183) is formed on the at least one region of the first conductivity type ([0048] and [0067]).
Considering claim 20, Yan discloses a method of forming an III-nitride semiconductor based heterojunction integrated circuit (IC), comprising (Figs. 1, 2, and 10A-10F):
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forming a substrate (102) ([0023]); a III-nitride semiconductor region located over the substrate, wherein the III- nitride semiconductor region (circular enclosed region in annotated Fig. 2 above) comprises a heterojunction comprising at least one two- dimensional carrier gas of a second conductivity type (Fig. 2, [0022], [0027], and [0069]); forming a power device comprising: a first terminal (D) operatively connected to the III-nitride semiconductor region; a second terminal (S) operatively connected to the Ill-nitride semiconductor region and laterally spaced from the first terminal (Fig. 2); a gate structure (G) located above the III-nitride semiconductor region and laterally spaced between the first and second terminals; and a control gate terminal (110) operatively connected to the gate structure, wherein the control gate terminal is configured such that a potential applied to the control gate terminal modulates and controls a current flow through the two- dimensional carrier gas between the first and second terminals ([0030] and [0070], note that the gate structure is formed such that a p-GaN layer is formed directly on the barrier layer 106 and then a metal gate layer (control gate) is formed over the p-GaN gate layer); forming a second device (rectangular enclosed region in the annotated Fig. 2 above) comprising at least one second two-dimensional carrier gas of the second conductivity type ([0022], [0027], and [0069]); an isolation region (162) between the power device and the second device such that the two dimensional carrier gas of the power device and the second two dimensional carrier gas of the second device are separated by the isolation region to form two distinctive active areas of two dimensional carrier gas (Fig. 2 and [0046]-[0049]); forming at least one region of a first conductivity type positioned laterally between an active area of the power device and an active area of the second device ([0046]-[0049], note that the one region of first conductivity type is also the isolation region), and forming a Schottky or ohmic metal contact (183) is on the at least one region of the first conductivity type ([0048] and [0067]).
Continuing to claim 2, Yan discloses wherein the at least one region of the first conductivity type is located within the isolation region (Fig. 2).
Referring to claim 3, Yan discloses wherein the at least one region of the first conductivity type is a carrier injector configured to inject carriers of the first conductivity type into the III-nitride semiconductor region ([0048]-[0049]).
Regarding claim 4, Yan discloses wherein the carrier injector laterally surrounds the second device (Fig. 1).
Pertaining to claim 5, Yan discloses wherein the carriers of the first conductivity type are holes ([0067]).
As to claim 6, Yan discloses comprising a terminal operatively connected to the Schottky or ohmic metal contact is formed on the at least one region of the first conductivity type, wherein the terminal is biased at a ground potential (Fig. 2 and [0048]-[0049]).
Concerning claim 9, Yan discloses comprising a terminal operatively connected to the Schottky or ohmic metal contact is formed on the at least one region of the first conductivity type, wherein the terminal is biased at a switching potential between a ground potential and a fixed positive bias, and wherein the terminal is biased at the switching potential by one of (i) the power device control signal; (ii) the drain potential of the power device; or (iii) a fraction of the drain potential of the power device via a potential divider ([0048]-[0049]).
Considering claim 10, Yan discloses wherein the III-nitride semiconductor region comprises an AIGaN barrier layer (106) and a GaN layer (104), and wherein the heterojunction is formed at a junction between the AIGaN barrier layer and the GaN layer, and wherein the GaN layer comprises a GaN buffer region and a GaN channel region ([0025]-[0026] and [0069]).
Continuing to claim 11, Yan discloses wherein the GaN buffer region is highly doped and the GaN channel region is unintentionally doped ([0025] an d[0034]).
Referring to claim 13, Yan discloses wherein either:(i) the carrier injector is formed on a GaN layer of the Ill-nitride semiconductor region; or (ii) the carrier injector is formed in a trench in a GaN layer of the Ill-nitride semiconductor region (Fig. 2).
Regarding claim 14, Yan discloses wherein the carrier injector is a region of highly p doped GaN, and wherein the carrier injector is formed on a AIGaN barrier layer of the III-nitride semiconductor region ([0025]-[0026], [0034], and [0069]).
Pertaining to claim 15, Yan discloses wherein the AIGaN barrier layer is partially recessed (Fig. 2).
As to claim 16, Yan discloses wherein the gate structure comprises a region of highly p doped GaN formed on a AIGaN barrier layer of the III-nitride semiconductor region, and wherein the control gate terminal is a Schottky or Ohmic metal contact formed on the highly p doped GaN ([0070]).
Concerning claim 17, Yan discloses wherein either:(i) the isolation region does not comprise the heterojunction comprising the at least one two-dimensional carrier gas of a second conductivity type; or (ii) the isolation region comprises a region of ion implantation, wherein the region is configured to reduce the conductivity of the at least one two-dimensional carrier gas by a factor of at least 100 ([0067]).
Considering claim 18, Yan discloses wherein the second device comprises one or more of:- an enhancement mode transistor; - a depletion mode transistor; - a capacitor; - a resistor; or - a diode ([0031]).
Referring to claim 19, Yan discloses wherein the isolation region comprises at least one shielding region, wherein the shielding region comprises an ohmic contact; and wherein the shielding region is biased at one of (i) a ground potential; (ii) a fixed bias; or (iii) a switching potential between a ground potential and a fixed bias ([0048]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20240047451 (Yan et al).
Regarding claim 7, Yan discloses comprising a terminal operatively connected to the Schottky or ohmic metal contact is formed on the at least one region of the first conductivity type, wherein the terminal is biased at a ground potential (Fig. 2 and [0048]-[0049]).
Yan does not disclose (in the embodiment as shown in Fig. 2) comprising a terminal operatively connected to the Schottky or ohmic metal contact is formed on the at least one region of the first conductivity type, wherein the terminal is biased at a fixed positive bias. However, Yan discloses other embodiments (Fig. 8) comprising a terminal operatively connected to the Schottky or ohmic metal contact is formed on the at least one region of the first conductivity type, wherein the terminal is biased at a fixed positive bias ([0054]-[0056] and [0062]-[0065]) and that such configuration yields improved device structure design and avoidance of the back gate effect in the nitride-based transistors of this configuration ([0005]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the embodiment of Fig. 2 such that a terminal operatively connected to the Schottky or ohmic metal contact is formed on the at least one region of the first conductivity type, wherein the terminal is biased at a fixed positive bias as seen with Fig. 8 of Yan in order to improve the device structure.
Pertaining to claim 8, Yan discloses wherein either:(i) the terminal is biased at the fixed positive bias by a DC rail; or (ii) the heterojunction IC comprises a potential divider configured to bias the terminal at a fraction of the DC rail ([0045]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20240047451 (Yan et al) as applied to claim 1 above, and further in view of Buffer transport mechanisms in intentionally carbon dope GaN heterojunction filed effect transistors (Uren et al).
As to claim 12, Yan discloses forming the GaN buffer region ([0025] and [0034]).
Yan does not disclose wherein the GaN buffer region is carbon doped. However Uren discloses in the field of GaN based heterojunction field effect transistors that a semi-insulating GaN layer is required before the final AlGaN barrier layer which induces the active two-dimensional electron gas (2DEG). In this paper, we analyze the impact of carbon doping of the GaN on transport mechanisms. Carbon results in the Fermi level being pinned about 0.9 eV above the valence band 2,3 and is the most commonly used dopant for GaN power devices delivering excellent control of leakage with high breakdown voltage (page 263505-1 column 1 lines 18-23). It would have been obvious to one of ordinary skill in the art to modify the GaN buffer layer of Yan to a carbon doped GaN buffer layer in order to achieve excellent control of leakage in the device as disclose by Uren.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20170098649 discloses a III-nitride semiconductor based transistor device that utilizes implantation in order to achieve isolation between III-nitride semiconductor based transistors (Fig. 1, [0017], and [0043]-[0045]) .
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 07/15/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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