Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/22/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 1-6 without traverse in the reply filed on 01/20/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lasiter et al US 20190259677 A1. Lasiter et al will be referenced to as Lasiter henceforth.
Regarding Claim 1,
Lasiter teaches:
“An electronic component, comprising (FIG. 10):
a first substrate (substrate 220, [0030]) having a first surface (annotated FIG. 10 #1) with a first region (annotated FIG. 10 #1) and a second region (annotated FIG. 10 #1), a plurality of first bumps provided in the first region (plurality of interconnects 225, [0030]), and zero or one or more second bumps provided in the second region (plurality of interconnects 227, [0030]), the number of second bumps being smaller than the number of first bumps (FIG. 10: there are 5 first bumps and 4 second bumps.);
and a second substrate (planarization layer 260, [0034]) having a second surface (annotated FIG. 10 #1) with a third region facing the first surface and the first region (annotated FIG. 10 #1) and a fourth region facing the second region (annotated FIG. 10 #1), a plurality of third bumps provided in the third region and in contact with the first bumps (plurality of interconnects 245, [0033]), zero or one or more fourth bumps provided in the fourth region and in contact with the second bumps (plurality of interconnects 263, [0034]), a third surface provided on a side opposite to the third region (planar surface A, [0092], FIG. 13 Stage 2: figures 10 and 13 are consistent with each other as they are not mutually exclusive.) and having a first distance from the second surface (FIG. 13 Stage 2), and a fourth surface provided on a side opposite to the fourth region and having a second distance from the second surface shorter than the first distance (planar surface B, [0092], FIG. 13 Stage 2), the number of fourth bumps being smaller than the number of third bumps (FIG. 10: There are 5 third bumps and 4 fourth bumps.). ”
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Annotated FIG. 10 #1
Regarding Claim 4,
Lasiter teaches:
“The electronic component according to claim 1, wherein the second distance is 90% or more of the first distance ([0092], FIG. 13 Stage 2: the height difference between planar surface A and planar surface B, the step up height, is a 10% difference. Therefore, the height to planar surface B is 90% the height to planar surface A as measured from a second surface.).”
Regarding Claim 6,
Lasiter teaches:
“The electronic component according to claim 1, wherein the first bumps are provided in an array in the first region (FIG. 5, FIG. 10: 247 is arranged in an array. Each 247 is in one to one correspondence with 225. Therefore, 225 is also arranged in an array.).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lasiter as applied to claims 1, 4, and 6 above, and further in view of Hsieh et al US 20240194646 A1. Hsieh et al will be referenced to as Hsieh henceforth. Hsieh has foreign priority to 2022-12-09.
Regarding Claim 2,
Lasiter teaches:
“The electronic component according to claim 1,”
Lasiter, alone, doesn’t substantially teach :
““wherein a third area of the third bump within a plane parallel to the second surface is smaller than a first area of the first bump within a plane parallel to the first surface.”
However, Hsieh teaches:
“wherein a third area of the third bump within a plane parallel to the second surface is smaller than a first area of the first bump within a plane parallel to the first surface (Hsieh: [0021], FIG. 1, FIG. 2: second bumps 150 have a larger cross-sectional area than metal pillars 140. This brings the advantage of being able to more easily and precisely bond chips together.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lasiter is modifiable in view of Hsieh by making the cross-sectional area of the first bumps larger than the cross-sectional area of the third bumps.
This is because Hsieh teaches that third bumps having an increased cross-sectional area compared to first bumps gives the advantage of being able to more easily and precisely bond chips together (Hsieh: [0021]).
Regarding Claim 3,
Lasiter/Hsieh teaches:
“The electronic component according to claim 1, wherein a fourth area of the fourth bump within a plane parallel to the second surface is smaller than a second area of the second bump within a plane parallel to the first surface (Lasiter/Hsieh: Hsieh: [0021], FIG. 1, FIG. 2: second bumps 150 have a larger cross-sectional area than metal pillars 140. This brings the advantage of being able to more easily and precisely bond chips together. One of ordinary skill in the art would implement this advantage by making the cross-sectional area of the second bumps larger than the cross-sectional area of the fourth bumps.).”
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lasiter as applied to claims 1, 4, and 6 above, and further in view of Kirby et al US 20210066207 A1. Kirby et al will be referenced to as Kirby henceforth.
Regarding Claim 5,
Lasiter teaches:
“The electronic component according to claim 1,”
Lasiter doesn’t substantially teach:
“wherein the second region includes a fifth region having one or more of the second bumps and a sixth region having no second bump, and the fourth region includes a seventh region having one or more of the fourth bumps and an eighth region having no fourth bump.”
However, Kirby teaches:
“wherein the second region includes a fifth region having one or more of the second bumps (Kirby: [0080], annotated FIG. 6B #1, FIG. 7A) and a sixth region having no second bump (Kirby: base plate, [0079], annotated FIG. 6B #1, FIG. 7A), and the fourth region includes a seventh region having one or more of the fourth bumps (Kirby: annotated FIG. 6B #1, FIG. 7A) and an eighth region having no fourth bump (Kirby: annotated FIG. 6B #1, FIG. 7A).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lasiter is modifiable in view of Kirby.
This is because Kirby teaches that base plates provide the advantage of distributing stress from any possible protrusions. This is advantageous as stress from unwanted protrusions may cause cracking in a semiconductor device rendering the device unusable.
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Annotated FIG. 6B #1
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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