Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/29/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1,
Claim 1 recites the limitations, “a third surface of the wiring substrate”, “a fourth surface of the wiring substrate”, and “the third surface and the fourth surface having a difference in level, forming a step structure.” which the Examiner finds to be indefinite. This is because it is not clear how the third surface and the fourth surface could have a difference in level and form a step structure as the wiring substrate does not have a difference in level:
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Applicant’s Annotated FIG. 1 #1
The Examiner considers two scenarios. The first is that the third surface and the fourth surface are not surfaces of the wiring substrate, but are surfaces of the resin layer. This is consistent with Applicant’s figure 1. The second scenario is that the third surface and the fourth surface are surfaces of the second substrate which is also consistent with Applicant’s figure 1. Because Applicant’s specification indicates that the third and fourth surfaces are surfaces of the sealing resin, the Examiner interprets the limitation according to the first scenario.
Further, Claim 1 is rejected because the limitation, “a third surface of the wiring substrate that is opposite to the third region of the second surface and has a first distance from the second surface (FIG. 13 Stage 2), and a fourth surface of the wiring substrate that is opposite to the fourth region of the second surface,” is found to be indefinite because it is not clear how the third surface is opposite to the third region nor how the fourth surface is opposite to the fourth region. For the term, “opposite” to be definite, the relative positions of the two items deemed opposite must be defined. For example, the third surface may be opposite to the third region relative to a horizontal/vertical line passing through the center of the device. From the Applicant’s specification [0042] and first figure, the Examiner interprets the term, “opposite” in the Applicant’s above limitation to mean opposite relative to a horizontal line passing through the center of the device. This is because the third surface is not opposite to the third region with respect to any vertical line and the fourth surface is not opposite to the fourth region with respect to any vertical line.
Regarding Claims 2-6, these claims depend upon claim 1 and are rejected for the same reasons.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lasiter et al US 20190259677 A1. Lasiter et al will be referenced to as Lasiter henceforth.
Regarding Claim 1,
Lasiter teaches:
“An electronic component, comprising ([0010], [0102], FIGs. 9A-9C: Parts not labeled in FIGs. 9A-9C are labeled in FIG. 4):
a first substrate (substrate 220, [0030]) having a first surface (annotated FIG. 9C #1) with a first region (annotated FIG. 9C #1) and a second region (annotated FIG. 9C #1), a plurality of first bumps provided in the first region (plurality of interconnects 225, [0030]: the interconnects which are located in the first region in FIG. 9C), and zero or one or more second bumps provided in the second region (plurality of interconnects 227, [0030]: the interconnects which are located in the second region in FIG. 9C), the number of second bumps being smaller than the number of first bumps (FIG. 9C);
and a second substrate (annotated FIG. 9C #2) having a wiring substrate (dielectric 242, [0031], FIG. 4, FIG. 9C: 242 is labeled in FIG. 4, but is also present in FIG. 9C) forming a second surface of the second substrate that faces the first surface (annotated FIG. 9C #1), the second surface with a third region facing(annotated FIG. 9C #1) and a fourth region facing the second region (annotated FIG. 9C #1), the wiring substrate having a plurality of third bumps provided in the third region (interconnects 263 (the subset of 263 in the third region), [0034], FIG. 9C) [[and]], the third bumps being in contact with the first bumps (FIG. 9C), and zero or one or more fourth bumps provided in the fourth region (interconnects 263 (the subset of 263 in the fourth region.), [0034], FIG. 9C) [[and]] the fourth bumps being in contact with the second bumps (annotated FIG. 9C #1), and the number of fourth bumps being smaller than the number of third bumps (annotated FIG. 9C #1: There are 4 third bumps and 3 fourth bumps.), and a sealing resin provided on the wiring substrate (polymer planarization layer 260, [0034]), the sealing resin sealing a semiconductor chip mounted on the wiring substrate ([0031]: The die 204 has an active side which is a front side in contact with dielectric 242. For a side of a device to be active, it must have active devices. An active device must have semiconductor chips.), and forming a third surface of the wiring substrate that is of the second surface (planar surface A, [0092], FIG. 13 Stage 2: figures 10 and 13 are consistent with each other as they are not mutually exclusive. The step-up height is above and proportional to the height of 204. Therefore, the step-up of 260 in FIG. 10 would be above die 204. And therefore above the third region.) and has a first distance from the second surface (FIG. 13 Stage 2), and a fourth surface of the wiring substrate that is of the second surface, and has a second distance from the second surface shorter than the first distance (planar surface B, [0092], FIG. 13 Stage 2), the third surface and the fourth surface having a difference in level, forming a step structure (FIG. 13 Stage 2). ”
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Annotated FIG. 9C #1
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Annotated FIG. 9C #2
Regarding Claim 4,
Lasiter teaches:
“The electronic component according to claim 1, wherein the second distance is 90% or more of the first distance ([0092], FIG. 13 Stage 2: The height difference between planar surface A and planar surface B, the step up height, is a 10% difference. Therefore, the height to planar surface B is 90% the height to planar surface A as measured from a second surface.).”
Regarding Claim 6,
Lasiter teaches:
“The electronic component according to claim 1, wherein the first bumps are provided in an array in the first region (FIG. 5, FIGs. 9A-9C: 247 is arranged in an array. Each 247 is in one to one correspondence with 225. Therefore, 225 is also arranged in an array.).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lasiter as applied to claims 1, 4, and 6 above, and further in view of Hsieh et al US 20240194646 A1. Hsieh et al will be referenced to as Hsieh henceforth. Hsieh has foreign priority to 2022-12-09.
Regarding Claim 2,
Lasiter teaches:
“The electronic component according to claim 1,”
Lasiter, alone, doesn’t substantially teach :
““wherein a third area of the third bump within a plane parallel to the second surface is smaller than a first area of the first bump within a plane parallel to the first surface.”
However, Hsieh teaches:
“wherein a third area of the third bump within a plane parallel to the second surface is smaller than a first area of the first bump within a plane parallel to the first surface (Hsieh: [0021], FIG. 1, FIG. 2: second bumps 150 have a larger cross-sectional area than metal pillars 140. This brings the advantage of being able to more easily and precisely bond chips together.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lasiter is modifiable in view of Hsieh by making the cross-sectional area of the first bumps larger than the cross-sectional area of the third bumps.
This is because Hsieh teaches that third bumps having an increased cross-sectional area compared to first bumps gives the advantage of being able to more easily and precisely bond chips together (Hsieh: [0021]).
Regarding Claim 3,
Lasiter/Hsieh teaches:
“The electronic component according to claim 1, wherein a fourth area of the fourth bump within a plane parallel to the second surface is smaller than a second area of the second bump within a plane parallel to the first surface (Lasiter/Hsieh: Hsieh: [0021], FIG. 1, FIG. 2: second bumps 150 have a larger cross-sectional area than metal pillars 140. This brings the advantage of being able to more easily and precisely bond chips together. One of ordinary skill in the art would implement this advantage by making the cross-sectional area of the second bumps larger than the cross-sectional area of the fourth bumps.).”
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lasiter as applied to claims 1, 4, and 6 above, and further in view of Kirby et al US 20210066207 A1. Kirby et al will be referenced to as Kirby henceforth.
Regarding Claim 5,
Lasiter teaches:
“The electronic component according to claim 1,”
Lasiter doesn’t substantially teach:
“wherein the second region includes a fifth region having one or more of the second bumps and a sixth region having no second bump, and the fourth region includes a seventh region having one or more of the fourth bumps and an eighth region having no fourth bump.”
However, Kirby teaches:
“wherein the second region includes a fifth region having one or more of the second bumps (Kirby: [0080], annotated FIG. 6B #1, FIG. 7A) and a sixth region having no second bump (Kirby: base plate, [0079], annotated FIG. 6B #1, FIG. 7A), and the fourth region includes a seventh region having one or more of the fourth bumps (Kirby: annotated FIG. 6B #1, FIG. 7A) and an eighth region having no fourth bump (Kirby: annotated FIG. 6B #1, FIG. 7A).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Lasiter is modifiable in view of Kirby.
This is because Kirby teaches that base plates provide the advantage of distributing stress from any possible protrusions. This is advantageous as stress from unwanted protrusions may cause cracking in a semiconductor device rendering the device unusable.
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Annotated FIG. 6B #1
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 102(a)(1) and 103 rejections.
Applicant substantively argues:
“Notably, in Lasiter, the dielectric layer 242, which is read as having the claimed "third region," is a part of the die 204”
The Examiner does not find this argument to be fully persuasive because 242 contains wires and supports a die 242 containing semiconductor chips. Therefore 242 is a wiring substrate.
Applicant further substantively argues,
“The planarization layer 260 of Lasiter is also provided for planarization (see also [0034]), and thus cannot be reasonably read as any "wiring substrate.”
The Examiner finds this argument to be fully persuasive as 260 does not support the die 204.
Applicant further substantively argues,
“Furthermore, the dielectric layer 242 of Lasiter cannot be reasonably read as the claimed "sealing resin," because the dielectric layer 242 is a part of the die 204 and does not have any sealing property. Therefore, any surface of the dielectric layer 242 cannot be reasonably read as the claimed "third surface."”
The Examiner finds this argument fully persuasive as 242 is a substrate and is not used as a sealant for the die 204. The Examiner notes that 260 is a polymer with a sealing property as 260 seals the die 204.
The Applicant further argues,
“" Moreover, the surface of the planarization layer 260 facing the PCB 1004 is flat and does not form any step structure as required by the claimed "third surface" and "fourth surface”
The Examiner notes that 260 is not flat in figure 13 step 2. The device 600, which is the device of FIG. 9C, which is cited in the Examiner’s current rejection of the claims may experience this manufacturing step by Lasiter [0092].
Because the Applicant has overcome the Examiner’s 102(a)(1) and 103 rejections, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a separate embodiment of Lasiter.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the following limitation:
“wherein the wiring substrate is electrically coupled to a pad, wherein the pad is electrically connected to the semiconductor chip through a bond wire”
It would overcome the current rejections for claim 1-6. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights