Prosecution Insights
Last updated: May 29, 2026
Application No. 18/453,720

PACKAGE ASSEMBLY FOR INTEGRATED CIRCUIT

Non-Final OA §102
Filed
Aug 22, 2023
Priority
Jul 20, 2023 — provisional 63/514,628
Examiner
GEYER, SCOTT B
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Cisco Technology Inc.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
668 granted / 710 resolved
+26.1% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
19 currently pending
Career history
727
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
27.5%
-12.5% vs TC avg
§102
42.5%
+2.5% vs TC avg
§112
13.5%
-26.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 710 resolved cases

Office Action

§102
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Group I (claims 1-12 and 17-24) in the reply filed on December 11, 2025 is acknowledged. Information Disclosure Statement The references cited within the IDS document submitted on August 22, 2023 has been considered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-5, 17-22, and 24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jiang et al. (US 2023/0352387 A1, hereinafter referred to as ‘Jiang’). As to claim 1, Jiang teaches an apparatus comprising: a plurality of packages (multi-layered structures above and below 303) of an integrated circuit (IC); a core via (306) extending between a first package of the plurality of packages and a second package of the plurality of packages; and a pad (e.g. 307a) electrically coupling the core via to the first package, wherein the pad comprises an oblong shape. See figure 3. As to claim 2, Jiang teaches an additional pad (307c) electrically coupling the core via to the second package. See figure 3. As to claim 3, Jiang teaches the additional pad comprises another oblong shape. See annotated figure below; the definition of oblong is a shape that deviates from a square, circular, or spherical form by elongation in one dimension, e.g. a rectangle. PNG media_image1.png 877 970 media_image1.png Greyscale As to claim 21, Jiang teaches the pad and the additional pad extend from the core via in opposite directions; i.e. they are on opposite sides of core layer (303). As to claim 22, Jiang teaches the pad and the additional pad are oriented crosswise with respect to one another; i.e. they are on opposite sides (across from each other) of core layer (303). As to claims 4 and 5, Jiang teaches a dielectric material (core layer 303, which can be bismaleimide triazine resin, see para. 0037) positioned between the first package and the second package, wherein the dielectric material (BT resin) comprises a dielectric constant that is below a threshold value, which can be between 1.5 and 3. See also teaching reference, Wang et al., cited on the attached form PTO-892. As to claim 17, Jiang teaches (in figure 3) an apparatus comprising: a first pad (307a) of a first package (multi-layered structure above core 303) of an integrated circuit (IC); a second pad (307c) of a second package (multi-layered structure below core 303) of the IC; and a core via (306) having a first end connected to the first pad and a second end connected to the second pad to electrically couple to the first package and to the second package, wherein at least one of the first pad and the second pad is oblong (see annotated figure on previous page, and explanation for oblong from the rejection of claim 3). As to claim 18, Jiang teaches wherein each of the first pad and the second pad is oblong, as shown in figure 3. As to claim 19, Jiang teaches wherein the first pad and the second pad extend from the core via in opposite directions; i.e. they are on opposite sides of core layer (303). As to claim 20, Jiang teaches wherein the first pad and the second pad are oriented crosswise with respect to one another; i.e. they are on opposite sides (across from each other) of core layer (303). As to claim 24, Jiang teaches a dielectric material (of core layer 303, BT resin) positioned between the first package and the second package of the IC, wherein the dielectric material comprises a dielectric constant that is below 3. Allowable Subject Matter Claims 6, 11, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not teach or suggest the disclosed invention regarding the apparatus of claim 1, wherein the pad comprises two arcuate portions and a linear portion extending between the two arcuate portions to form the oblong shape, as recited within claim 6. The prior art of record does not teach or suggest the disclosed invention regarding the apparatus of claim 1, wherein the microvia is offset from the pad, and the IC comprises a connection pad that is connected to the microvia and to the pad to electrically couple the microvia and the pad to one another, as recited within claim 11. The prior art of record does not teach or suggest the disclosed invention regarding the apparatus of claim 1, wherein the first package comprises a plurality of stitching vias positioned around the pad, and a quantity of the plurality of stitching vias is greater than a threshold quantity, as recited within claim 12. Claims 7-10 are also objected to as being dependent upon claim 6; claim 23 is also objected to as being dependent upon claim 12. Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000. /SCOTT B GEYER/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Aug 22, 2023
Application Filed
Apr 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12635385
DISPLAY DEVICE
2y 6m to grant Granted May 19, 2026
Patent 12622117
IMAGE DISPLAY DEVICE MANUFACTURING METHOD AND IMAGE DISPLAY DEVICE
3y 2m to grant Granted May 05, 2026
Patent 12622298
ELECTRONIC PACKAGE, PACKAGING SUBSTRATE AND FABRICATING METHOD THEREOF
2y 11m to grant Granted May 05, 2026
Patent 12622253
SEMICONDUCTOR DEVICE WITH THROUGH VIAS OF VARIOUS SHAPES AND METHOD OF MANUFACTURING THE SAME
2y 10m to grant Granted May 05, 2026
Patent 12610674
DEEP ULTRAVIOLET LIGHT-EMITTING DIODE
3y 3m to grant Granted Apr 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.4%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 710 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month