Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, and 3-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi et al. (Pub. No.: US 2010/00252904 A1).
Regarding Claim 1, Takahashi et al. discloses a semiconductor device comprising: a semiconductor substrate having a drift layer of a first conductivity type formed therein (Par. 0036-0037; Figs. 1-2 & 18-19 – semiconductor substrate 50; drift layer 1 (N-type impurity region)); an active region in which a semiconductor element is formed in the semiconductor substrate (Par. 0036-0037; Figs. 1-2 & 18-19 – not explicitly labeled); a termination region, which is a region outside the active region in the semiconductor substrate (Par. 0036-0037; Figs. 1-2 & 18-19 – shown but not explicitly labeled); a well layer of a second conductivity type formed in the surface portion of the semiconductor substrate in the termination region, in which an impurity concentration of the second conductivity type decreases toward the outside of the semiconductor substrate (Par. 0095-0096; Fig. 19 – P-type impurity regions 23a to 23c together could be considered as the “well layer”; regarding the well-layer this prior art states “P-type impurity regions 23a to 23c have, at the surface of substrate 50, depths and P-type impurity concentrations decreasing from P-well 2 toward P-type RESURF layer 18”); and
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a channel stopper layer of the first conductivity type formed in the surface portion of the semiconductor substrate, being more outside than the well layer is (Par. 0036-0037; Figs. 1-2 & 18-19 – channel stopper region 4 (N-type)), wherein the termination region includes an alleviating region adjacent to the active region and having the well layer formed therein (Par. 0095-0096; Fig. 19 – the region corresponding to the well layer 23 could be considered as the “alleviating region”),
a RESURF' region positioned outside the alleviating region and having the well layer formed more shallowly than that in the alleviating region (Par. 0095-0096; Fig. 19 – the region corresponding to the P-type RESURF layer 18 could be considered as the “RESURF region”), a channel stopper region positioned outside the RESURF region and having the channel stopper layer formed therein (Par. 0095-0096; Fig. 19 – the region corresponding to the channel stopper layer 4 could be considered as the “channel stopper region”), an electrode formed on the alleviating region through an interlayer insulating film (Par. 0039-0040; Fig. 19 – plate 17a which is formed, at least partially, on the alleviating region through an interlayer insulating film 19 could be considered as the electrode), a channel stopper electrode connected to the channel stopper layer (Par. 0039-0040; Fig. 19 – channel stopper electrode 12), and a semi-insulating film covering the electrode and the channel stopper electrode and electrically connecting the electrode and the channel stopper electrode (Par. 0039-0040, 0067; Fig. 19 – semi-insulating film 15), wherein the termination region further includes at least one field plate electrode formed on the RESURF region with the interlayer insulating film interposed between the RESURF region and the at least one field plate electrode (Par. 0039-0040; Fig. 19 – field plate electrode 17b and/or 17c), the at least one field plate electrode is not formed on the alleviating region (Par. 0039-0040; Fig. 19 – field plate electrode 17c is not formed on the alleviating region), and the semi-insulating film covers the electrode, the at least one field plate electrode and the channel stopper electrode and electrically connects the electrode, the at least one field plate electrode, and the channel stopper to each other (Par. 0039-0040, 0067; Fig. 19 – semi-insulating film 15).
Regarding Claim 3, Takahashi et al., as applied to claim 1, discloses the semiconductor device, wherein intervals of the electrode, the at least one field plate electrode, and the channel stopper electrode are even (Fig. 19).
Regarding Claim 4, Takahashi et al., as applied to claim 1, discloses the semiconductor device, wherein the at least one field plate electrodes comprises a plurality of field plate electrodes, and widths of the plurality of field plate electrodes are even (Par. 0039-0040; Fig. 19 – field plate electrodes 17b, 17c etc.).
Regarding Claim 5, Takahashi et al., as applied to claim 1, discloses the semiconductor device, wherein the electrode, the field plate electrodes and the channel stopper electrode are made of a same conductive material (Par. 0066; Fig. 19 - the electrode 17a, the field plate electrodes 17b-17c and the channel stopper electrode 12 are all made of a same conductive material, such as aluminum).
Claims 1, 4-6 & 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawakami et al. (Pub. No.: WO 2015/104900 A1 – machine translation).
Regarding Claim 1, Kawakami et al. discloses a semiconductor device comprising: a semiconductor substrate having a drift layer of a first conductivity type formed therein (Par. 0031-0033; Fig. 17 – drift layer 11 (N-type conductivity); an active region in which a semiconductor element is formed in the semiconductor substrate (Par. 0031-0033; Fig. 17 – active region comprising base layer 12); a termination region, which is a region outside the active region in the semiconductor substrate (Par. 0031-0033 & 0051; Fig. 17 – the region on the right of the base layer 12 could be considered as the termination region); a well layer of a second conductivity type formed in the surface portion of the semiconductor substrate in the termination region, in which an impurity concentration of the second conductivity type decreases toward the outside of the semiconductor substrate (Par. 0031-0039; Fig. 17 – electric field relaxation layer 13 of P-type conductivity could be considered as the well layer); and a channel stopper layer of the first conductivity type formed in the surface portion of the semiconductor substrate, being more outside than the well layer is (Par. 0031-0039; Fig. 17 – channel stopper layer 14 (N-type conductivity)), wherein the termination region includes an alleviating region adjacent to the active region and having the well layer formed therein (Par. 0031-0039, 0084; Fig. 17 (also see annotated Fig. 17)), a RESURF' region positioned outside the alleviating region and having the well layer formed more shallowly than that in the alleviating region (Par. 0031-0039, 0084; Fig. 17 (also see annotated Fig. 17) – the region corresponding to the well layer 13 that is directly under the wiring group 40b and extends up to the left edge of the well layer 13 corresponding to the right edge of the alleviating region could be considered as the “RESURF region”), a channel stopper region positioned outside the RESURF region and having the channel stopper layer formed therein (Par. 0031-0039, 0084; Fig. 17 – the region corresponding to the channel stopper layer 14 could be considered as the “channel stopper region”),
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an electrode formed on the alleviating region through an interlayer insulating film (Par. 0031-0039; Fig. 17 – plate 20 which is formed, at least partially, on the alleviating region through an interlayer insulating film 19 could be considered as the electrode), a channel stopper electrode connected to the channel stopper layer (Par. 0031-0039; Fig. 17 – channel stopper electrode 16), and a semi-insulating film covering the electrode and the channel stopper electrode and electrically connecting the electrode and the channel stopper electrode (Par. 0031-0039; Fig. 17 – semi-insulating film 23), wherein the termination region further includes at least one field plate electrode formed on the RESURF region with the interlayer insulating film interposed between the RESURF region and the at least one field plate electrode (Par. 0072-0080; Fig. 17 –field plate electrodes 44b, 45b etc.), the at least one field plate electrode is not formed on the alleviating region ((Par. 0031-0039, 0072-0080; Fig. 17 field plate electrodes 44b, 45b are not formed on the alleviating region), and the semi-insulating film covers the electrode, the at least one field plate electrode and the channel stopper electrode and electrically connects the electrode, the at least one field plate electrode, and the channel stopper to each other(Par. 0031-0039, 0072-0080; Fig. 17 – semi-insulating film 23).
Regarding Claim 4, Kawakami et al., as applied to claim 1, discloses the semiconductor device, wherein the at least one field plate electrodes comprises a plurality of field plate electrodes, and widths of the plurality of field plate electrodes are even (Par. 0072-0080; Fig. 17 –field plate electrodes 44b, 45b etc.).
Regarding Claim 5, Kawakami et al., as applied to claim 1, discloses the semiconductor device, wherein the electrode, the field plate electrodes and the channel stopper electrode are made of a same conductive material (Par. 0169; Fig. 17 - the electrode, the field plate electrodes and the channel stopper electrode could all be potentially formed of aluminum or copper or alloys).
Regarding Claim 6, Kawakami et al., as applied to claim 1, discloses the semiconductor device, wherein an outer end of the electrode projects into the RESURF region (Par. 0090; Fig. 17 (please also see annotated Fig. 17 attached to the rejection of claim 1 above); also see rejection of claim 1), and a length by which the electrode projects into the RESURE region is 0 µm or more and 30 µm or less (Par. 0090; Fig. 17 (please also see annotated Fig. 17 attached to the rejection of claim 1 above) – the width of the electrode 20 is 30 µm; so in light of the rejection of claim 1, the length by which the electrode 20 projects into the RESURE region is more than 0 µm and less than 30 µm).
Regarding Claim 8, Kawakami et al., as applied to claim 1, at least implicitly. discloses the semiconductor device, wherein resistivity of the semi-insulating film is 1×1012 Ω.cm or less. (Par. 0015; Fig. 17 – this prior art teaches that the sheet resistance is at least 1×108 Ω/sq which implies that the resistivity of the semi-insulating film is 1×1012 Ω.cm or less unless the semi-insulating film is absurdly thick).
Regarding Claim 9, Kawakami et al., as applied to claim 1, discloses the semiconductor device, further comprising an insulating layer formed on the semi-insulating film (Par. 0031-0039; Fig. 17 – insulating layer 24, semi-insulating layer 23).
Regarding Claim 10, Kawakami et al., as applied to claim 1, discloses the semiconductor device, further comprising a surface protection film covering the semi-insulating film so as to fill concave and convex portions present on an upper surface of the semi-insulating film (Par. 0031-0039; Fig. 17 – surface protection film 24, semi-insulating layer 23).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 7 is rejected under 35 U.S.C. 103 as obvious over Kawakami et al. (Pub. No.: WO 2015/104900 A1 – machine translation), as applied to claim 1, further in view of Takahashi (Pub. No.: US 2013/0161645 A1).
Regarding Claim 7, Kawakami et al., as applied to claim 1, does not disclose the semiconductor device, wherein an inner end of the channel stopper electrode projects into the RESURF region, and a length by which the channel stopper electrode projects into the RESURF region is 0 µm or more and 30 µm or less.
However, Takahashi teaches the semiconductor device, wherein an inner end of the channel stopper electrode projects into the RESURF region (Par. 0034-0043; Fig. 2 - channel stopper electrode 36; RESURF region is the region corresponding to the RESURF layer 24). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Takahashi to adapt the semiconductor device, wherein an inner end of the channel stopper electrode of projects into the RESURF region of Kawakami et al. in order to further tune the electric field near the end of RESURF layer to increase the withstand voltage. The projection length of the channel stopper electrode into the RESRF region affects the breakdown voltage. Too much or too little projection can adversely affect the breakdown voltage. The optimum projection depending on doping, oxide thickness etc. ensures the maximum breakdown voltage.
In summary, modified Kawakami et al. discloses the claimed invention except for the semiconductor device, wherein a length by which the channel stopper electrode projects into the RESURF region is 0 µm or more and 30 µm or less. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to the semiconductor device, wherein a length by which the channel stopper electrode projects into the RESURF region is 0 µm or more and 30 µm or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Response to Arguments
Applicants’ arguments filed on 03/04/2026 have been fully considered but they are not found to be persuasive. Please see the rejections above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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03/16/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893