DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Claims 1 – 18, drawn to an apparatus, in the reply filed on 15 December 2025 is acknowledged.
Claims 19 & 20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 15 December 2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 22 August 2023 has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15 – 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 15 – 17 recite the limitation "second member". However, there is insufficient antecedent basis for this limitation in these claims.
For the purposes of examination, “second member” will be interpreted as “second body”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 7, 9, 11, & 16 – 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by AMANO (US 20230411202 A1).
Regarding Claim 1,
AMANO discloses:
A semiconductor manufacturing apparatus (Fig. 2: 20; Par. 38), comprising:
a plurality of clamping portions (Fig. 2 & 5A: Each housing of a given 53 and its corresponding outermost vertically opposing pair of pairs of 53as—Par. 43—is a clamping portion of a first type—hereinafter denoted 53/53a4—and each remaining vertically opposing pair of 53as is a clamping portion of a second type—hereinafter denoted 53a2) positioned around an outer circumferential position (Fig. 2 & 5B: edge of 1) of a wafer (Fig. 5B: 1; Par. 29) and configured to pull a sheet (Fig. 5B & 5C: 11; Par. Par. 34), to which the wafer is mounted, outwardly from a central portion (Fig. 3 & 5C: radial center of 1) of the wafer, each clamping portion including a first rotating body (Fig. 2 & 5A: the upper 53a—which rotates, Par. 43—for a given 53a2—hereinafter denoted 53a2_1—and the 53U housing/upper pair of 53a—which rotates—for a given 53/53a4—hereinafter denoted 53/53a4_1) paired with a second body (Fig. 2 & 5A: the lower 53a for a given 53a2—hereinafter denoted 53a2_2—and the 53D housing/lower pair of 53a for a given 53/53a4—hereinafter denoted 53/53a4_2) for clamping the sheet;
(Fig. 2 & 5B: The 53a2 and 53/53a4 are positioned around the edge of 1 and configured to pull 11—Par. 53 & 66—to which 1 is mounted, outwardly from the radial center of 1, each 53a2 and 53/53a4, respectively, includes 53a2_1 and 53/53a4_1, respectively, paired with 53a2_2 and 53/53a4_2, respectively, for clamping the sheet—Par. 40 – 43.)
and a control unit (Fig. 2: 100; Par. 51) configured to control the rotation of each first rotating body of the plurality of clamping portions to pull the sheet outwardly.
(Fig. 2: 100 is configured to expand 11 by pulling 11 outwardly, Par. 38 – 51, and the individual “53a are configured to freely rotate in a direction orthogonal to a direction in which [11] is expanded, and are able to expand [11] while clamping [11]”, Par. 43. That is, as 100 actively controls the expansion of 11 in D1, 100 passively controls the rotation of each 53a in D2 and vice versa. As such, 100 is configured to control the rotation of each 53a2_1 and 53/53a4_1 of the plurality of 53a2 and 53/53a4, respectively, to pull 11 outwardly.)
Regarding Claim 2,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1,
wherein the clamping portions are disposed concentrically with respect to the wafer.
(Fig. 2 & 5B: 53a2 and 53/53a4 are disposed to form a rectangle where said rectangle and 1 share a common center, the radial center of 1. Thus, 53a2 and 53/53a4 are disposed concentrically with respect to 1.)
Regarding Claim 3,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1,
wherein the clamping portions are at different distances from the central portion of the wafer.
(Fig. 2: 53a2 and 53/53a4 are at different distances from the radial center of 1.)
Regarding Claim 4,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1,
wherein clamping portions adjacent to each other are at different distances from the central portion of the wafer.
(Fig. 2: The 53a2s adjacent to each other are at different distances from the radial center of the wafer.)
Regarding Claim 5,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 4,
wherein the adjacent clamping portions overlap each other when viewed radially from the central portion of the wafer.
(Fig. 2 & 5B: Due to the close arrangement of the individual 53as, the adjacent 53a2s overlap each other when viewed radially from the radial center of the wafer.)
Regarding Claim 6,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1,
wherein a first group of clamping portions (Fig. 2: The 53a2 and 53/53a4 with the axes of symmetry for their individual 53as parallel to D1, hereinafter denoted G1) have first rotating bodies that pull the sheet along a first direction (Fig. 2 & 5C: D1) parallel to a surface (Fig. 5B & 5C: The top surface of 1) of the wafer, and a second group of clamping portions (Fig. 2: The 53a2 and 53/53a4 with the axes of symmetry for their individual 53as parallel to D2, hereinafter denoted G2) have first rotating bodies that pull the sheet a second direction (Fig. 2: D2) parallel to the surface of the wafer and different from the first direction.
(Fig. 2: G1 has 53a2_1 and 53/53a4_1 that—in part—pull 11 along D1 parallel to the top surface of 1, and G2 has 53a2_1 and 53/53a4_1 that—in part—pull 11 along D2 parallel to the top surface of 1 where D1 is different from D2, Par. 45.)
Regarding Claim 7,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1,
wherein the control unit controls the rotation of the first rotating body for each clamping portion so that a load on the plurality of clamping portions is uniform.
(Fig. 2: 100 passively controls the rotation of 53a2_1 and 53/53a4_1 for each 53a2 and 53/53a4, respectively—as described in Claim 1—so that the load on the plurality of 53a2s and 53/53a4s orthogonal to their respective directions of expansion is zero—as the individual “53a are configured to freely rotate in a direction orthogonal to a direction in which [11] is expanded”, Par. 43—and, thus, uniform.)
Regarding Claim 9,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1, further comprising:
a heating unit (Fig. 2 & 3: 30; Par. 38) configured to heat portions of the sheet beyond the outer circumference of the wafer while the first rotating bodies are being rotated to pull the sheet outwardly from the central portion of the wafer.
(30 is configured to be moved into contact with 11 to cool 11—Fig. 5B; Par. 56—before 53a2_1 and 53/53a4_1 are rotated to pull 11 outwardly from the radial center of 1 while 11 remains in contact with 30—Fig. 5C; Par. 66. However, Par. 38 teaches 30 provides a means of heating or cooling 11, and Fig. 5C shows 30 remains in contact with 11 while 11 is being pulled outwardly. Therefore, 30 inherently possess the ability to heat 11—including portions of 11 beyond the outer circumference of 1—while 53a2_1 and 53/53a4_1 are being rotated to pull 11 outwardly from the radial center of 1, MPEP 2114 I.)
Regarding Claim 11,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1, further comprising:
a load detection unit (Fig. 2: 60; Par. 49) to detect a load of a first rotating body of one of the plurality of clamping portions,
(Fig. 2: 60 detects the temperature distribution of 1—Par. 49—which is a load of 11 and, thus, a load of the 53a2_1s and 53/53a4_1s due to the direct contact between these elements. As such, 60—indirectly—detects a load of the 53a2_1s and 53/53a4_1s of the plurality of 53a2s and 53/53a4s, respectively.)
wherein the control unit controls the rotation of the first rotating body of the one of the plurality of clamping portion based on a detection result from the load detection unit.
(100 controls the rotation of the 53a2_1s and 53/53a4_1s of the plurality of 53a2s and 53/53a4s, respectively, based on the temperature distribution detection result from 100, Par. 51)
Regarding Claim 16,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1,
wherein, in at least one clamping portion, a shape or size of the first rotating body is different from a shape or size of the second body.
(Fig. 2: In a given 53/53a4, the shape and size of the housing of 53 of 53/53a4_1 is different from the shape and size of the 53a of 53/53a4_2.)
Regarding Claim 17,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1,
wherein the second body is a rotating body.
(Fig. 2: 53a2_2 and 53/53a4_2 are rotating bodies, as the individual 53a rotate; Par. 43.)
Regarding Claim 18,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1,
wherein the control unit controls each of the plurality of clamping portions by feedback control.
(100 controls each of the plurality of 53a2 and 53/53a4 by using feedback from 60—Par. 51. Thus, 100 controls each of the plurality of 53a2 and 53/53a4 by feedback control.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over AMANO.
Regarding Claim 8,
AMANO discloses:
The semiconductor manufacturing apparatus according to claim 1,
wherein the control unit controls the rotation of the first rotating body for each clamping portion (As described in Claim 1)…
AMANO, however, does not disclose:
wherein the control unit controls the rotation of the first rotating body for each clamping portion according to a shape of chips (Fig. 5C: C; Par. 67) formed on the wafer.
Regardless, though not explicitly disclosed, 20 is capable of moving opposing pairs of 53a2 and 53/53a4 independently by the description provided for 20 in Par. 37 – 46. That is, 20 is capable of pulling 11 outwardly along D1 and D2 independently, which provides the ability for 100 to control the separation of the Cs formed on 1 to be greater along D1 than D2, or vice versa. In turn, this provides the ability for 100 to control the separation of the Cs formed on 1 such that a sufficient separation—which is partially dependent upon the shape of the Cs formed on 1—between adjacent Cs is generated. That is, though not explicitly disclosed, 100 is capable of controlling the rotation of 53a2_1 and 53/53a4_1 for each 53a2 and 53/53a4, respectively, according to the shape of the Cs formed on 1, MPEP 2114 II.
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to enable the control unit to control the rotation of the first rotating body for each clamping portion according to a shape of chips formed on the wafer in AMANO for the further advantage of preventing—by providing a sufficient separation—the adjacent chips formed on the wafer from colliding with and damaging each other (AMANO Par. 3).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over AMANO in view of ZHAO (US 20210028063 A1).
Regarding Claim 10,
AMANO does not disclose:
The semiconductor manufacturing apparatus according to claim 9,
wherein the heating unit is rotatable about an axis that passes through substantially the center portion of the wafer.
ZHAO, however, discloses:
wherein the heating unit (Fig. 5: 382; Par. 63) is rotatable about an axis (Fig. 5: Z) that passes through substantially the center portion of the wafer (Fig. 5 & 15: the radial center of 2; Par. 32).
(Fig. 5 & 15: 382 is rotatable about Z that passes through substantially the radial center of 2, Par. 62 & 63.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of AMANO with those of ZHAO to enable the heating unit to be rotatable about an axis that passes through substantially the center portion of the wafer in AMANO according to the teachings of ZHAO, as these inventions are from the same field of endeavor, and the heating units of AMANO and ZHAO are recognized in the art for the same purpose of heating portions of the sheet beyond the outer circumference of the wafer while the first rotating bodies are being rotated to pull the sheet outwardly from the central portion of the wafer (MPEP 2144.06).
Claims 12, 14, & 15 are rejected under 35 U.S.C. 103 as being unpatentable over AMANO in view of KAWASAKI (JP 2016111229 A).
Regarding Claim 12,
AMANO does not disclose:
The semiconductor manufacturing apparatus according to claim 1, further comprising:
a chip interval detection unit to detect an interval between chips formed from the wafer, wherein the control unit controls the rotation of the first rotating bodies based on a detection result from the chip interval detection unit.
KAWASAKI, however, discloses:
a chip interval detection unit (Fig. 1: 60; Pag. 2 Par. 1) to detect an interval between chips (Fig. 1: CP; Pag. 2 Par. 1) formed from the wafer (Fig. 1: WF; Pag. 2 Par. 1), wherein the control unit controls the rotation of the first rotating bodies (Fig. 1: 53; Pag. 2 Par. 5) is based on a detection result from the chip interval detection unit.
(Fig. 1: 60 detects an interval between the CPs formed from WF, wherein the rotation of 53—as part of adjusting the interval between the CPs—is based on a detection result from 60, Pag. 3 Par. 1. While a control unit is not explicitly disclosed, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a controller as a means to control the claimed function.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of AMANO with those of KAWASAKI to enable a chip interval detection unit to detect an interval between chips formed from the wafer, wherein the control unit controls the rotation of the first rotating bodies based on a detection result from the chip interval detection unit in AMANO according to the teachings of KAWASAKI for the further advantage of providing increased control over chip separation as a means of preventing damage to the chips (AMANO Par. 3).
Regarding Claim 14,
AMANO does not disclose:
The semiconductor manufacturing apparatus according to claim 12,
wherein the chip interval detection unit is a camera.
KAWASAKI, however, discloses:
wherein the chip interval detection unit is a camera.
(60 provides an “imaging means”, Pag. 2 Par. 1, which constitutes a camera.
Regarding Claim 15,
AMANO does not disclose:
The semiconductor manufacturing apparatus according to claim 1,
wherein the first rotating bodies are a different material than the second body.
KAWASAKI, however, discloses:
wherein the first rotating bodies (Fig. 1: 53; Pag. 4 Par. 7) are a different material than the second body (Fig. 1: 33; Pag. 4 Par. 7).
(Fig. 1: 53 may be made of metal and 33 may be made of resin.)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of AMANO with those of KAWASAKI to enable the first rotating bodies to be made of a different material than the second body in AMANO according to the teachings of KAWASAKI, as AMANO does not disclose a material for either the first rotating bodies or the second body. Therefore, one of ordinary skill in the art would look to the prior art for such materials recognized for their suitability and intended purpose (MPEP 2144.07). Further, the materials of KAWASAKI meet these criteria, as they are used in the same context and for the same reason as the corresponding undisclosed materials of AMANO.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over AMANO in view of KAWASAKI and in further view of YAMAWAKI (US 20230207344 A1)
Regarding Claim 13,
AMANO and KAWASAKI do not disclose:
The semiconductor manufacturing apparatus according to claim 12,
wherein the chip interval detection unit is a laser scanning unit.
YAMAWAKI, however, discloses:
wherein the chip interval detection unit (Fig. 3: 57; Par. 50) is a laser scanning unit (Par. 50).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of AMANO in view of KAWASAKI with those of YAMAWAKI to enable the chip interval detection unit to be a laser scanning unit in AMANO in view of KAWASAKI according to the teachings of YAMAWAKI, as these inventions are from the same field of endeavor, and these detection units of AMANO in view of KAWASAKI and YAMAWAKI are recognized in the art for the same purpose of detecting and measuring wafer and chip spacing and positioning (YAMAWAKI Par. 50; MPEP 2144.06).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898