DETAILED ACTION
This action is responsive to the election received on 12/17/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species B in the reply filed on 12/17/2025 is acknowledged.
Claim(s) 11 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claim(s) 8 and 9 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. An interview with attorney of record Joseph Buczynski on 02/20/2026 confirmed that claims 8 and 9 appear to be drawn to the non-elected species and claim 7 is drawn to the elected species. Claims 1-6 and 10 appear to be generic to the identified species. Additional details are included in the attached interview summary (PTO-413).
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in JAPAN on 11/01/2022.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/22/2023, 08/08/2025, 08/13/2025, and 11/13/2025 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 is recites the limitation “the fourth semiconductor layer is formed below the contact region such that the depth is partially deep”. The term “partially” in claim 3 is a relative term which renders the claim indefinite. The term “partially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Partially” is defined (Merriam Webster Online Dictionary) as “to some extent : in some degree”. In the context of the claim, it is unclear to what depth the fourth semiconductor layer needs to be formed in order to be considered “partially deep”. A depth identified as “partially deep” may be relative to other component(s) (i.e. deeper in one region than a first element but shallower than a second element such that it is “partially” deep) or require a certain depth range (i.e. a specific depth in nanometers or micrometers where the depth has an upper and lower limit) to be considered “partially deep”. For this reason, claim 3 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this examination, a fourth semiconductor layer will be considered partially deep if it extends to a greater depth in the region directly under the contact region based on Figure 5 of the instant application wherein the fourth semiconductor layer (#24) is deeper in the area under the contact region (#27).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-7, and 10 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2022/0216314 A1; Harada et al.; 07/2022; (“Harada”).
Regarding Claim 1. Harada discloses A semiconductor device (#100, Figures 1A-1F, various views and cross sections of a semiconductor device according to [0009]-[0014]) in which a transistor (#70, Figure 1A, transistor unit) and a diode (#80, Figure 1A, diode unit) are formed on a common semiconductor substrate (#10, Figure 1B, semiconductor substrate in which #70 and #80 are formed), wherein
the semiconductor substrate (#10) includes
a transistor region in which the transistor is formed (Figures 1A-1C, region encompassed by the bracket(s) for #70 encompassing the formed transistor), and
a diode region in which the diode is formed (Figures 1A-1C, region encompassed by the bracket(s) for #80 encompassing the formed diode),
the diode region includes
a first conductivity type first semiconductor layer (#82, Figure 1B, N+ type cathode region of semiconductor substrate) provided on a second main surface side of the semiconductor substrate (#23, Figure 1B, #82 is formed on rear surface #23 of #10),
a first conductivity type second semiconductor layer (#18 and #20, Figure 1B, N- type drift region and N type buffer region of semiconductor substrate) provided on the first semiconductor layer (Figure 1B, the combination of #18 and #20 is formed directly on #82),
a second conductivity type third semiconductor layer (#14, Figure 1B, P- type base region of the semiconductor substrate) provided closer to a first main surface side of the semiconductor substrate (#21, Figure 1B, front surface of #10) than the second semiconductor layer (Figure 1B, #14 is formed to be closer to #21 than the combination of #18 and #20 is to #21),
a first main electrode that applies a first potential to the diode (#52, Figure 1B, emitter electrode which may apply a bias to the diode #80 through direct contact to the p-type region of the diode),
a second main electrode that applies a second potential to the diode (#24, Figure 1B, collector electrode which may apply a second bias to the diode #80 through direct contact to the n-type region of the diode),
a plurality of diode trench gates (#30s and #40s, Figure 1A, dummy trench portions and gate trench portions) provided to reach the second semiconductor layer from the first main surface of the semiconductor substrate (Figure 1B, #30s and #40s reach #18 from the surface #21 of #10), and
a contact region (#27, Figure 1B, trench contact) provided in an upper layer portion of the third semiconductor layer (Figures 1D and 1F, #27 is formed to be contained within an upper portion of #13), and the contact region is composed of a conductor material ([0069], “Each of the trench contacts 27 has a conductive material”) embedded in a recess portion provided in the third semiconductor layer (Figures 1B, 1D, and 1F, each #27 is embedded in a recess which is provided to be contained within #14).
Regarding Claim 2. Harada discloses The semiconductor device according to claim 1, wherein
the diode region further includes a second conductivity type fourth semiconductor layer (#19 and #15, Figure 1B, p+ type contact layer and contact region of the semiconductor substrate) selectively provided in an upper layer portion of the third semiconductor layer (Figure 1B, the combination of #19 and #15 are selectively present in the upper portion of #14), and
the fourth semiconductor layer has
an impurity concentration of the second conductivity type (Figure 1B, #15 and #19 are both p-type), which is higher than that of the third semiconductor layer ([0060], “The contact regions 15 are regions of the second conductivity type having a higher doping concentration than the base region 14”; [0072], “contact layer 19 is a region of the second conductivity type having a higher doping concentration than the base region 14”), and
a depth of the contact region is shallower than that of the fourth semiconductor layer (Figure 1B, the depth of #27 is shallower than the depth of the combination of #15 and #19).
Regarding Claim 3. Harada discloses The semiconductor device according to claim 2, wherein the fourth semiconductor layer is formed below the contact region such that the depth is partially deep (Figures 1B and 1F, in accordance with the 35 U.S.C. 112(b) rejection above, the fourth semiconductor layer (#15 and #19) is considered partially deep as it extends to a greater depth in the region directly under the contact region (#27)).
Regarding Claim 6. Harada discloses The semiconductor device according to claim 1, wherein
the plurality of diode trench gates (#30s and #40s) include
a first diode trench gate provided at a boundary between the transistor region and the diode region (Figure 1B, the #30 located at the vertical boundary between the regions bounded by #70 and #80) and
a second diode trench gate other than the first diode trench gate (Figure 1B, the #30 located at the right side of the region bounded by #80),
the first diode trench gate is covered with an interlayer insulating film (#38, Figure 1B, interlayer dielectric film) provided between the first diode trench gate and the first main electrode (Figure 1B, #30 located at the boundary between #70 and #80 is covered by #38 which is provided between #30 and #52), and
the second diode trench gate is covered with the first main electrode (Figure 1B, #30 on the right side of #80 is covered at least partially by #52, noting here that “covered” does not require direct contact).
Regarding Claim 7. Harada discloses The semiconductor device according to claim 1, wherein the contact region is provided between adjacent diode trench gates in a stripe shape in parallel with the diode trench gates (Figure 1A, #27s are provided between adjacent #30s and #40s in a stripe shape that extends in parallel with the #30s and #40s).
Regarding Claim 10. Harada discloses The semiconductor device according to claim 2, wherein
the fourth semiconductor layer is provided at a boundary between the transistor region and the diode region (Figure 1A, #15 is provided at a boundary between #80 and #70 on either side of the #30), and
the fourth semiconductor layer of the transistor region is continuously provided along a diode trench gate provided at the boundary (Figure 1B, the #15 on the #70 side of the boundary is continuously provided along a portion of the sidewall of the #30 located at the boundary on the #70 side).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0216314 A1; Harada et al.; 07/2022; (“Harada”) as applied to claim 1 above, and further in view of CN 112563321 A; Soneda et al.; 03/2021; (“Soneda”).
Regarding Claim 4. Harada discloses The semiconductor device according to claim 1.
Harada does not explicitly disclose that the third semiconductor layer has a depth distribution such that a depth becomes deepest below the contact region.
However, Soneda teaches a semiconductor device (Figure 3) comprising a transistor region (#1a, IGBT region) and a diode section (#1b, diode region) in a semiconductor substrate (#1) wherein the diode region comprises a first conductivity type first semiconductor layer (#11, N type cathode layer) on a lower surface (Figure 3, #11 is on a lower surface of #1), a first conductivity type second semiconductor layer (Figure 3, N type buffer layer), and a second conductivity type third semiconductor layer (#12, P type anode layer) located nearer to the top surface of the substrate (Figure 3, top surface of #1), and a plurality of diode trench gates (#13c and #7c, trench and groove electrodes) provided to reach the second semiconductor layer (#1) from the top surface (Figure 3, #7c and #13c reach #1 from the top surface), and a contact region (#22, Figure 3, second contact layer), the third semiconductor layer has a depth distribution such that a depth becomes deepest below the contact region (Figure 3, #12 has a depth distribution such that the depth of #12 is formed to be at its deepest in the diode region #1b below the contact regions #22).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider depth distribution of the third semiconductor layer to be deepest underneath the contact layers in Harada, as was done by Soneda, since doing so makes it possible to reduce recovery loss and not block the electronic discharge after the follow current (see paragraph 2 on page 12 through paragraph 1 on page 13 of Soneda)
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0216314 A1; Harada et al.; 07/2022; (“Harada”) as applied to claim 1 above, and further in view of US 2023/0029909 A1; Naito, Tatsuya; 02/2023; (“Naito”).
Regarding Claim 5. Harada discloses The semiconductor device according to claim 1.
Harada does not disclose that the first semiconductor layer is provided alternately with a second conductivity type fifth semiconductor layer in an array direction of the plurality of diode trench gates.
However, Naito teaches a semiconductor device (#100, Figures 1A-2E are various views and cross sections of the semiconductor device #100 according to [0015]-[0021]) comprising a transistor region (#70) and a diode section (#80) in a semiconductor substrate (#10) wherein the diode region comprises a first conductivity type first semiconductor layer (#82, N+ type cathode region) on a lower surface (#23), a first conductivity type second semiconductor layer (#20 and #18, N type buffer and drift regions), and a second conductivity type third semiconductor layer (#14, P type base region) located nearer to the top surface of the substrate (#21), and a plurality of diode trench gates (#30s and #40s, gate trench parts and dummy trench parts) provided to reach the second semiconductor layer (#18) from the top surface (#21), and the first semiconductor layer (#82) is provided alternately with a second conductivity type fifth semiconductor layer (#83, Figure 2D, P type cathode regions) in an array direction of the plurality of diode trench gates (Figures 2D and 2E, #82 and #83 are provided alternately to one another along the array direction (Y-direction) of the plurality of #30s and #40s).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing the alternating first conductivity type first semiconductor layer with a second conductivity type fifth semiconductor layer along the array direction of the trench gates in the device of Harada, as was done by Naito, since doing so makes it possible to suppress voltage overshoot upon reverse recovery of the diode section (see [0161] and [0309] of Naito)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2024/0006520 A1; Naito, Tatsuya; 01/2024 – Figures 2 and 3A disclose a semiconductor device wherein the diode region (#80) includes a plurality of contact regions (#55) extending into the device to provide a lower resistance path for holes and suppress latch-up (see [0130]).
US 2023/0299077 A1; Muramatsu et al.; 09/2023 – Figures 1A-1E disclose a semiconductor device wherein the diode region (#80) includes a plurality of contact regions (#60) extending into the device to provide enhanced ability to withstand destructive breakdown such as latch-up due to the presence of the minority carrier (see [0084]).
US 2021/0234027 A1; Yoshida, Soichi; 07/2021 – Figures 2A, 2B, and 3 disclose a semiconductor device wherein the diode region (#80) includes a plurality of contact regions (#54) extending into the device to reduce reverse recovery losses in the diode portion (see [0070]).
US 2022/0013645 A1; Shimosawa et al.; 01/2022 – Figures 1 through 6 disclose a semiconductor device wherein the diode region (#80) includes a plurality of contact regions (#60) extending into the device to improve the breakdown withstand capability such as a latch up withstand capability due to minority carriers (see [0079]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TYLER J WIEGAND/Examiner, Art Unit 2812