DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
1. This office action is in response to applicant's Arguments/ Remarks filed on 06/04/2026. Claims 1-10, 12-16 and n19-23 are pending; claims 11 and 17-18 are canceled.
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 02/04/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
3. Applicant’s arguments with respect to claim(s) 1-10, 12-16 and 19-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
4. Claim(s) 1, 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carpineto et al (U.S. Patent No. US 2005/0026583 A1) in view of Kobayashi et al (U.S. Patent No. US 2013/0136213 A1) further in view of Krivokapic (U.S. Patent No. US 2006/0148437 A1)
Regarding claim 1, Carpineto et al discloses an apparatus (figure 3, a receiver 38; paragraph 0038), comprising: an RF receiver front end that offers at least three distinct performance modes (figure 3, a LNA 42; paragraph 0032, “… the LNA-mixer of a Direct Conversion Receiver, or similar receiver, is placed in one of three states: a high gain state 30, intermediate gain state 32, or low gain state 34); a logic circuit to specify a performance mode of the three distinct performance modes at least partially responsive to an input signal power state (figure 3, a gain control system 40; paragraphs 0033 and 0041, “…gain control system 40 controls the gain of LNA 42 and VGA 44”); and an automatic radio controller to set a performance mode of the RF receiver front end to the specified one of the three distinct performance modes (paragraph 0038, “…gain control system 40 controls the gain of LNA 42 and VGA 44”; and paragraphs 0038 and 0041-0042 “… in addition to HIGH_GAIN and LOW_GAIN signals, the gain control system 40 can output an intermediate gain signal (INT_GAIN). “), wherein the RF receiver front end includes: a signal processing chain comprising a baseband amplifier (figure 3, a VGA 44; paragraph 0038); wherein a performance setting is determined based on a power state of an input signal to the RF receiver front end (paragraph 0044, “…the useful signal power level is read and the AGC determines gain levels for the LNA 42 (LNA_gain) and VGA 44 (BB_gain) based on the power level of the useful signal”) and a performance defining setting is determined based on the determined performance setting (paragraph 0044, “…the useful signal power level is read and the AGC determines gain levels for the LNA 42 (LNA_gain) and VGA 44 (BB_gain) based on the power level of the useful signal. Using standard techniques, the AGC will determine whether the LNA 42 should be at HIGH_GAIN (if useful signal is low or very low) or LOW_GAIN (if useful signal is high)),
Carpineto et al does not disclose a circuit to selectively bypass the baseband amplifier and silent to wherein the performance defining setting is for direct-current bias current and a clock rate of a performance block of a signal processing chain of the RF receiver front end.
Kobayashi et al discloses a receiver includes a circuit to selectively bypass a baseband amplifier (figure 1, a VGA 107, paragraph 0031, “…The bypass switch section 111 includes switches SWb1 and SWb set to open and close a path in which an output of the VGA 107f of a first stage bypasses the VGA 107r of a post-stage and is inputted to the ADC 109.” ; and paragraph 0032, “…switch controller 113 controls turning on and off states of the isolation switches SWf and SWr and the switches SWb1 and SWb of the bypass switch section 111 in accordance with a control signal from the DC offset controller 115 so that the outputs of the VGAs may be respectively inputted to the ADC 109 without passing through the VGAs of the post-stages”)
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Kobayashi et al in to the apparatus of Carpineto et al, such that the apparatus could be comprised a circuit to selectively bypass the baseband amplifier if desired, in order to allow amplitude to meet a full-scale of the ADC as taught by Kobayashi et al (paragraph 0032 ).
Carpineto et al in view of Kobayashi et al silent to wherein the performance defining setting is for direct-current bias current and a clock rate of a performance block of a signal processing chain of the RF receiver front end.
Krivokapic discloses a receiver includes a performance defining setting is for direct-current bias current (figure 1, a first current control circuit 50 (1): paragraph 0027 and a clock rate of a performance block of a signal processing chain of the RF receiver front end (paragraphs 0027 and 0065, “…voltage controlled oscillator of the frequency synthesizer 24 through which current consumption by the VCO is adjusted”)
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Krivokapic in to the apparatus of Carpineto et al in view of Kobayashi et al , such that the receiver could be included a performance defining setting is for direct-current bias current and a clock rate of a performance block of a signal processing chain of the RF receiver front end in order to allow for step-wise or continuous adjustments to be made in the bias current supplied to the associated receiver component as taught by Krivokapic (paragraph 0028 ).
Regarding claim 12, Carpineto et al in view of Kobayashi et al and Krivokapic discloses the apparatus of claim 1. Carpineto et al discloses the apparatus comprising: an automatic radio controller to dynamically set one or more parameters of power-defining blocks of the RF receiver front end within one of the at least three distinct performance modes (paragraph 0038 and 0044, “…state 62, the useful signal power level is read and the AGC determines gain levels for the LNA 42 (LNA_gain) and VGA 44 (BB_gain) based on the power level of the useful signal.”)
Regarding claim 14, claim 14 is similar in scope to the claim 1 except in method form and thus the rejection to claim 1 hereinabove is also applicable to claim 14.
5. Claim(s) 2-3, 9,13, 19-21 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carpineto et al (U.S. Patent No. US 2005/0026583 A1) in view of Kobayashi et al (U.S. Patent No. US 2013/0136213 A1) further in view of Krivokapic (U.S. Patent No. US 2006/0148437 A1) further in view of Waxman (U.S. Patent No. US 2007/0223626 A1).
Regarding claim 2, Carpineto et al in view of Kobayashi et al and Krivokapic discloses the apparatus of claim 1. Carpineto et al discloses wherein the distinct performance modes include blocker tolerance settings (paragraph 0042, “…. First, two different thresholds could be used in the blocker detect signal, responsive to the gain level of the LNA 42. When the LNA_gain is set to a HIGH_GAIN level, a first threshold could be used and when LNA_gain is set to an INT_GAIN level, a second, lower, threshold could be used.”).
Carpineto et al in view of Kobayashi et al and Krivokapic does not disclose wherein the distinct performance modes include different sensitivity settings
Krivokapic discloses a distinct performance modes include different sensitivity settings.
Waxman discloses a distinct performance modes include different sensitivity settings (paragraphs 007-0018).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Carpineto et al in view of Kobayashi et al and Krivokapic with the teachings of Waxman, such that to include a different sensitivity settings in a distinct performance modes of receiver in order to provide a reduction of power consumption in a mobile wireless device as taught by Waxman (abstract ).
Regarding claim 3, Carpineto et al in view of Kobayashi et al and Krivokapic discloses the apparatus of claim 1. Carpineto et al discloses wherein the RF receiver front end offers one or more further distinct performance modes (paragraphs 0041-0042).
Carpineto et al in view of Kobayashi et al and Krivokapic silent to wherein respective performance associated with the one or more further distinct performance modes are between the highest sensitivity and the lowest sensitivity.
Waxman discloses RF receiver front end offers one or more further distinct performance modes (figure 2, steps220, 230 and 240; paragraphs 0017-0018) , and wherein respective performance associated with the one or more further distinct performance modes are between the highest sensitivity and the lowest sensitivity (figure 2, step 230, paragraph 018, “..the current controlling the noise figure of the LNA may be set 230 to a medium control level to obtain mid-range receiver sensitivity.” ).
Regarding claim 9, Carpineto et al in view of Kobayashi et al and Krivokapic discloses the apparatus of claim 1. Carpineto et al in view of Kobayashi et al and Krivokapic silent to wherein the logic circuit includes: input signal power state definitions that include one or more thresholds associated with input signal power states; and performance setting definitions that includes one or more performance settings associated with input signal power states.
Waxman discloses an input signal power state definitions that includes one or more thresholds associated with input signal power states; and performance setting definitions that includes one or more performance settings associated with input signal power states (paragraphs 0017-0018).
Regarding claim 13, Carpineto et al in view of Kobayashi et al and Krivokapic discloses the apparatus of claim 1. Carpineto et al in view of Kobayashi et al and Krivokapic silent to wherein the logic circuit to specify a default performance mode, a performance setting associated with the default performance mode lower than a performance setting associated with the specified one of the three distinct performance modes.
Waxman discloses a default performance mode, a performance setting associated with the default performance mode lower than a performance setting associated with the specified one of the three distinct performance modes (paragraphs 0017-0018, “… RSSI is less than a threshold minimum”).
Regarding claim 19, Carpineto et al in view of Kobayashi et al and Krivokapic discloses the method of claim 14. Waxman discloses the method comprising: applying the determined performance defining setting to the RF receiver front end (paragraphs 0017-0018).
Regarding claim 20, and as applied to the claim 14 above, claim 20 is similar in scope to the claim 2 except in method form and thus the rejection to claim 2 hereinabove is also applicable to claim 20.
Regarding claim 21, and as applied to the claim 14 above, claim 21 is similar in scope to the claim 13 except in method form and thus the rejection to claim 13 hereinabove is also applicable to claim 21.
Regarding claim 23, Carpineto et al in view of Kobayashi et al and Krivokapic discloses the apparatus of claim 1. Carpineto et al discloses the method of claim 14. Carpineto et al in view of Kobayashi et al and Krivokapic silent to wherein the set one of at least three distinct performance modes offered by the RF receiver front end is a default performance mode.
Waxman discloses set one of at least three distinct performance modes offered by the RF receiver front end is a default performance mode (paragraphs 0017-0018, “… RSSI is less than a threshold minimum”).
6. Claim(s) 4-8 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carpineto et al (U.S. Patent No. US 2005/0026583 A1) in view of Kobayashi et al (U.S. Patent No. US 2013/0136213 A1) further in view of Krivokapic (U.S. Patent No. US 2006/0148437 A1) further in view of Waxman (U.S. Patent No. US 2007/0223626 A1) further in view of Riley et al (U.S. Patent No. US 2011/0084878 A1).
Regarding claim 4, Carpineto et al in view of Kobayashi et al and Krivokapic discloses the apparatus of claim 1. Carpineto et al discloses wherein the logic circuit to: obtain a value representative of a power level of an input signal to the RF receiver front end (paragraphs 0041-0042).
Carpineto et al in view of Kobayashi et al and Krivokapic silent to compare the value representative of the power level of the input signal to one or more thresholds, the one or more thresholds being probabilistic-based thresholds; and determine the input signal power state at least partially responsive to the comparison.
Waxman discloses obtaining a value representative of a power level of an input signal to the RF receiver front end (figure 2, step 210; paragraph 0016); compare the value representative of the power level of the input signal to one or more thresholds (figure 2, steps 215,225 and 235; paragraphs 0017-0018); and determine the input signal power state at least partially responsive to the comparison (paragraphs 0017-0018).
Carpineto et al in view of Kobayashi et al, Krivokapic and Waxman does not disclose the one or more thresholds being probabilistic-based thresholds.
Riley et al discloses thresholds can be probabilistic-based thresholds (paragraph 0066).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Riley et al in to the apparatus of Carpineto et al in view of Kobayashi et al, Krivokapic and Waxman, such that the one or more thresholds could be probabilistic-based thresholds for the purpose of signal strength measurement decision process as taught by Riley et al (paragraphs 0038 and 0066).
Regarding claim 5, Carpineto et al in view of Kobayashi et al, Krivokapic, Waxman and Riley et al discloses the apparatus of claim 4. Carpineto et al discloses wherein the logic circuit to: choose the one or more thresholds at least partially based on an indication of RF receiver front end mode (paragraph 0042, “…Two alternatives could be used to accommodate blocker detection at the INT_GAIN level. First, two different thresholds could be used in the blocker detect signal, responsive to the gain level of the LNA 42. When the LNA_gain is set to a HIGH_GAIN level, a first threshold could be used and when LNA_gain is set to an INT_GAIN level, a second, lower, threshold could be used.”). Waxman also discloses wherein the logic circuit to: choose the one or more thresholds at least partially based on an indication of RF receiver front end mode (paragraphs 0017-0018).
Regarding claim 6, Carpineto et al in view of Kobayashi et al, Krivokapic, Waxman and Riley et al discloses the apparatus of claim 4. Waxman discloses wherein the logic circuit to: determine a performance setting at least partially based on the input signal power state, the determined performance setting associated with the performance mode (paragraphs 0017-0018).
Regarding claim 7, Carpineto et al in view of Kobayashi et al, Krivokapic, Waxman and Riley et al discloses the apparatus of claim 6. Carpineto et al discloses wherein the performance defining setting is for one or more of a gain, a direct-current bias current, a bandwidth, or a clock rate of a performance defining block of a signal processing chain of the RF receiver front end (paragraphs 0041-0042).
Regarding claim 8, Carpineto et al in view of Kobayashi et al, Krivokapic, Waxman and Riley et al discloses the apparatus of claim 6. Carpineto et al discloses comprising an automatic radio controller to: determine a performance defining setting at least partially based on the determined performance setting; and apply the determined performance defining setting to the RF receiver front end (paragraphs 0041-0042).
Regarding claim 15, and as applied to the claim 14 above, claim 15 is similar in scope to the claim 4 except in method form and thus the rejection to claim 4 hereinabove is also applicable to claim 15.
Regarding claim 16, Carpineto et al in view of Kobayashi et al, Krivokapic, Waxman and Riley et al discloses the method of claim 15. Waxman discloses choosing the one or more thresholds at least partially based on an indication of RF receiver front end mode (paragraphs 0017-0018); Riley et al discloses the one or more thresholds being probabilistic-based thresholds(paragraph 0066).
7. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carpineto et al (U.S. Patent No. US 2005/0026583 A1) in view of Kobayashi et al (U.S. Patent No. US 2013/0136213 A1) further in view of Krivokapic (U.S. Patent No. US 2006/0148437 A1) further in view of in view of Sobchak et al (U.S. Patent No. US 2007/0086547A1).
Regarding claim 10, Carpineto et al in view of Kobayashi et al and Krivokapic discloses the apparatus of claim 1. Carpineto et al discloses wherein the RF receiver front end includes a signal processing chain comprising: a low-noise amplifier; a mixer (figure 3, the LNA 42 and a mixer 48; paragraph 0038).
Carpineto et al in view of Kobayashi et al and Krivokapic does not disclose an intermediate frequency (IF) amplifier with built-in low pass filter; and an analog-to-digital converter (ADC).
Sobchak et al discloses RF receiver front end includes a disclose an intermediate frequency (IF) amplifier 111, a pass filter 115; and an analog-to-digital converter (ADC) (figure 1, an intermediate frequency (IF) amplifier with built-in low pass filter; and an analog-to-digital converter (ADC) 117; paragraphs 0019-0020).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include an intermediate frequency (IF) amplifier with built-in low pass filter; and an analog-to-digital converter (ADC) in a receiver of Sobchak et al in to the receiver of Carpineto et al in view of Kobayashi et al and Krivokapic in order to provide a gain control signal corresponding to a wideband signal level as taught by Sobchak et al (paragraph 0019 ).
8. Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Carpineto et al (U.S. Patent No. US 2005/0026583 A1) in view of Kobayashi et al (U.S. Patent No. US 2013/0136213 A1) further in view of Krivokapic (U.S. Patent No. US 2006/0148437 A1) further in view of Waxman (U.S. Patent No. US 2007/0223626 A1) further in view of Rahman et al (U.S. Patent No. US 2008/0165899 A1).
Regarding claim 22, Carpineto et al in view of Kobayashi et al, Krivokapic and Waxman discloses the method of claim 21. Waxman discloses wherein the setting the performance mode of the RF receiver front end to the default performance mode comprises: setting the performance mode of the RF receiver front end to the default performance mode (paragraphs 0017-0018.
Carpineto et al in view of Kobayashi et al, Krivokapic and Waxman silent to the RF receiver front end to the default performance mode at least partially responsive to an indication of: a power-on, a power-on reset, or a reset.
Rahman et al discloses setting a performance mode of the RF receiver front end to a default performance mode at least partially responsive to an indication of: a power-on, a power-on reset, or a reset (paragraph 0034).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to use the teachings of Rahman et al in to the method of Carpineto et al in view of Kobayashi et al, Krivokapic and Waxman, such that a default performance mode could be indicted at least partially responsive to: a power-on, a power-on reset, or a reset in order to provide an improved performance of the receiver under static channel conditions as well as under fading channel conditions as taught by Rahman et al (paragraph 0042 ).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FATUMA G SHERIF whose telephone number is (571)270-7189. The examiner can normally be reached 10am - 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PAN YUWEN can be reached at 571-272-7855. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FATUMA G SHERIF/ Examiner, Art Unit 2649
/YUWEN PAN/ Supervisory Patent Examiner, Art Unit 2649
Prosecution Insights