DETAILED ACTION
This action is responsive to the following: the request for continued examination, the amendment to claims and the remarks made in amendment filed on January 23, 2026.
Claims 1-3 and 5-20 are pending. Claim 4 is cancelled. Claims 1, 16, and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on January 23, 2026 has been entered. Claims 1-3, 5-20 remain pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 23, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi et al (US 20050006696) in view of Kidoh et al (US 20090321813).
Regarding Independent Claim 1, Noguchi and Kidoh teach an AND type flash memory (Fig. 27: 45), comprising a memory cell array, wherein the memory cell array comprises a plurality of memory cells (Fig. 27: M0-M15) electrically connected in parallel between a source line (Fig. 27: SL) and a bit line (Fig. 27: BL),
a plurality of parallel and elongated diffusion regions (Fig. 1: 2, 3) are formed in the memory cell array,
shallow trench isolations (Fig. 20: 64) extending along a column direction and formed between the diffusion regions;
the plurality of memory cells connected in parallel respectively comprising a gate (Fig. 1: 4) and a charge accumulation layer (Fig. 1: 5), wheren the gate is disposed between the diffusion regions (Fig. 1: 2, 3) opposite to each other, the charge accumulation layer serves as a gate insulating film, and is capable of storing charges, and the charge accumulation layer comprises at least three or more insulating layers (Fig. 1: 62, 61, 64), wherein the charge accumulation layer (Fig. 20: 5) is separated by the shallow trench isolation (Fig. 20: 64) relative to each memory cell in a row direction (Fig. 20: Row Direction; para 152),
However, Noguchi fails to teach the charge accumulation layer extends in a column direction and is shared by the memory cells adjacent in the column direction.
Kidoh teaches the charge accumulation layer (Fig. 10: 33) extends in a column direction and is shared by the memory cells adjacent in the column direction (para 80 “the charge storage layer 33 is formed along the side surface of the through hole 30, and continuously formed across a plurality of memory cells arranged in the Z direction”).
Continuous shared charge storage layers are advantageous because they reduce the number of process steps and number of masks required in manufacturing.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kidoh to the teachings of Noguchi to produce an AND type memory where the cells have a shared charge storage layer in the column direction.
Regarding Claim 2, Noguchi and Kidoh teach the limitations of Claim 1. Noguchi further teaches wherein the charge accumulation layer (Fig. 1: 5) comprises a nitride layer (para 5) for storing charges.
Regarding Claim 3, Noguchi and Kidoh teach the limitations of Claim 2. Noguchi further teaches wherein the charge accumulation layer (Fig. 1: 5, 61, 62) comprises the nitride layer between an upper insulating layer (Fig. 1: 63) and a lower insulating layer (Fig. 1: 4).
Regarding Claim 5, Noguchi and Kidoh teach the limitations of Claim 1. Noguchi further teaches wherein the charge accumulation layer (Fig. 14: 5) is separated relative to each memory cell (para 152).
Regarding Claim 6, Noguchi and Kidoh teach the limitations of Claim 1. Noguchi further teaches wherein the charge accumulation layer (Fig. 1: 5) accumulates charges tunneled from a channel when a program voltage is applied to the gate of the selected memory cell (para 70).
Regarding Claim 7, Noguchi and Kidoh teach the limitations of Claim 1. Noguchi further teaches wherein when a reference voltage is applied to the gate of the selected memory cell and an erase voltage is applied to a well region, the charge accumulation layer (Fig. 1) releases the accumulated charges to a channel through tunneling, or recombine accumulated electrons with holes tunneled from the channel (para 77) .
Regarding Claim 8, Noguchi and Kidoh teach the limitations of Claim 1. Noguchi further teaches wherein the memory cell array (Fig. 27: 45) further comprises a selection transistor (Fig. 27: S2) of a source line (Fig. 27: SL) side and a selection transistor (Fig. 27: S1) of a bit line (Fig. 27: BL) side, the selection transistor of the source line side is configured to selectively connect one of the diffusion regions common to a block of n memory cells connected in parallel to the source line (Fig. 27: GSL), and the selection transistor of the bit line side is configured to selectively connect the other diffusion region common to the block to the bit line (Fig. 27: SSL),
when the selection transistor (Fig. 27: GSL) of the source line side is turned on, one of the diffusion regions of the block is electrically connected to the source line (Fig. 27: SL), and when the selection transistor of the bit line (Fig. 27: SSL) side is turned on, the other diffusion region of the block is electrically connected to the bit line (Fig. 27: BL).
Regarding Claim 11, Noguchi and Kidoh teach the limitations of claim 8. Noguchi further teaches wherein one of the diffusion regions (Fig. 28: 15, S2, 10GSL) of the selection transistor of the source line side is electrically connected to one of the diffusion regions of the memory cell (Fig. 28: M15, 10WL15), and the other diffusion region is electrically connected to the source line (Fig. 28: 15s, CSL) through a conductive contact member,
one of the diffusion regions (Fig. 28: 15, S2, 10SSL) of the selection transistor of the bit line side is in common with the other diffusion region of the memory cell (Fig. 28: M0, 10WL0), and the other diffusion region (Fig. 28: 15d, CBL) is electrically connected to the bit line through a conductive contact member.
Regarding Independent Claim 16, Noguchi teaches a programming method, adapted to an AND type flash memory (Fig. 27: 45), wherein the AND type flash memory comprises a memory cell array, the memory cell array comprises a plurality of memory cells (Fig. 27: M0-M15) electrically connected in parallel between a source line (Fig. 27: SL) and a bit line (Fig. 27: BL), wherein
a plurality of parallel and elongated diffusion regions (Fig. 1: 2, 3) are formed in the memory cell array,
shallow trench isolations (Fig. 20: 64) extending along a column direction99 and formed between the diffusion regions;
the plurality of memory cells connected in parallel respectively comprise a gate (Fig. 1: 4) and a charge accumulation layer (Fig. 1: 5), the gate is disposed between the diffusion regions (Fig. 1: 2, 3) opposite to each other, the charge accumulation layer serves as a gate insulating film, and comprises at least three or more insulating layers (Fig. 1: 62, 61, 64) , wherein the charge accumulation layer (Fig. 14: 5) by the shallow trench isolation (Fig. 20: 64) relative to each memory cell in a row direction (Fig. 20: Row Direction; para 152),
a program voltage is applied to the gate of a selected memory cell, and a reference voltage is applied to a channel, thereby accumulating charges tunneled from the channel in the charge accumulation layer (para 87).
However, Noguchi fails to teach the charge accumulation layer extends in a column direction and is shared by the memory cells adjacent in the column direction.
Kidoh teaches the charge accumulation layer (Fig. 10: 33) extends in a column direction and is shared by the memory cells adjacent in the column direction (para 80 “the charge storage layer 33 is formed along the side surface of the through hole 30, and continuously formed across a plurality of memory cells arranged in the Z direction”).
Continuous shared charge storage layers are advantageous because they reduce the number of process steps and number of masks required in manufacturing.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kidoh to the teachings of Noguchi to produce a programming method for AND type memory where the cells have a shared charge storage layer in the column direction.
Regarding Independent Claim 19, Noguchi teaches an erasing method, adapted to an AND type flash memory (Fig. 27: 45), wherein the AND type flash memory comprises a memory cell array, the memory cell array comprises a plurality of memory cells (Fig. 27: M0-M15) electrically connected in parallel between a source line (Fig. 27: SL) and a bit line (Fig. 27: BL), wherein
a plurality of parallel and elongated diffusion regions (Fig. 1: 2, 3) are formed in the memory cell array,
shallow trench isolations (Fig. 20: 64) extending along a column direction and formed between the diffusion regions;
the plurality of memory cells connected in parallel respectively comprise a gate (Fig. 1: 4) and a charge accumulation layer (Fig. 1: 5), the gate is disposed between the diffusion regions (Fig. 1: 2, 3) opposite to each other, and the charge accumulation layer serves as a gate insulating film, and comprises at least three or more insulating layers (Fig. 1: 62, 61, 64), wherein the charge accumulation layer (Fig. 14: 5) is separated relative to each memory cell in a row direction (Fig. 20: Row Direction; para 152) by the shallow trench isolation (Fig. 20: 64),
a reference voltage is applied to the gate of a selected memory cell, and an erase voltage is applied to a well comprising a channel, and charges accumulated in the charge accumulation layer are released to the channel through tunneling (para 77).
However, Noguchi fails to teach the charge accumulation layer extends in a column direction and is shared by the memory cells adjacent in the column direction.
Kidoh teaches the charge accumulation layer (Fig. 10: 33) extends in a column direction and is shared by the memory cells adjacent in the column direction (para 80 “the charge storage layer 33 is formed along the side surface of the through hole 30, and continuously formed across a plurality of memory cells arranged in the Z direction”).
Continuous shared charge storage layers are advantageous because they reduce the number of process steps and number of masks required in manufacturing.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kidoh to the teachings of Noguchi to produce a programming method for AND type memory where the cells have a shared charge storage layer in the column direction.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (US 20050006696) and Kidoh et al (US 20090321813) in view of Kanamitsu et al (US 20050164442).
Regarding Claim 9, Noguchi and Kidoh teach the limitations of claim 8.
However, Noguchi fails to teach selection transistors at either end of the array which connect one side of the parallel resistors to either the source line or the bit line.
Kanamitsu teaches an AND type flash memory (Fig. 1: MM) where the memory cells are arranged in parallel with between two local bit lines (Fig. 1: BL) which connect to global bit lines (Fig. 1: GBL) by means of selection transistors (Fig 1: ST) at both ends.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the invention to apply the teachings of Kanamitsu to the teachings of Noguchi to produce an AND type flash memory array that teaches the limitations of claim 8 and has selection transistors on either end of the memory to connect the one side of the cells in parallel to the source line and the other side to the bit line when selected.
Regarding Claim 10, Noguchi and Kanamitsu teach the limitations of Claim 9.
Noguchi further teaches wherein each gate of the n memory cells in the block is respectively connected to a word line (Fig. 27: WL0-WL15) extending along a row direction (Fig. 27: Row Direction) on the memory cell array, the first selection control line and the second selection control line extend parallel to the word line (Fig. 28: 10WL0-10WL15, 10GSL, 10SSL).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (US 20050006696) and Kidoh et al (US 20090321813) in view of Mina et al. (US 8611158).Noguchi show the AND-type memory unit circuit schematic in Figure 27. Noguchi also show the AND-type memory unit plan-view layout in Figure 28. As illustrated, the “selection transistor of the source line side” (Figs. 27, 28: S2) and the “selection transistor of the bit line side” (Figs. 27, 28: S1) appear to be typical NMOS transistors.
As typical NMOS transistors, Noguchi is silent to their “selection transistor of the source line side” and “selection transistor of the bit line side” each comprising “a charge accumulation layer serving as a gate insulating film and other insulating films,” as claimed.
However, Mina teach a related non-volatile memory unit (in NAND-type) that utilizes “selection transistor of the source line side” (Fig. 2: 204) and “selection transistor of the bit line side” (Fig. 2: 214) each comprising “a charge accumulation layer serving as a gate insulating film and other insulating films,” (see Fig. 2: gate insulating films 204a that includes charge accumulation layer 204b for the source line side selection transistor 204 and for the bit line side selection transistor 214). Mina further explain that parasitic effects can arise because of voltage differences between the select transistors’ gates and the adjacent memory cells that undesirably cause electrons to be injected into the isolation oxides (col. 2, lines 31-37), a problem that is irreversible (see col. 2, lines 63-65). Mina’s disclosure is focused on solving that problem, and notably includes detailed explanations of offsetting and managing the threshold voltages of the select transistors (see col. 9, line 10- col. 10, line 34), which permits correct reading of the data (col. 10, lines 12-15 and 27-30) by avoiding the parasitic effects that lead to incorrect reading of data (see col. 2, lines 60-62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Mina to the teachings of Noguchi such that the select transistors on the source-side and bit-line side each have “a charge accumulation layer serving as a gate insulating film and other insulating films” so that their threshold voltage can be offset or managed to improve read operations as explained by Mina.
Claims 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (US 20050006696) and Kidoh et al (US 20090321813) in view of Yeh et al (US 20060007732).
Regarding Claim 13, Noguchi and Kidoh teach the limitations of claim 8. Noguchi further teaches a programming control part (Fig. 38: 76).
However, Noguchi fails to teach floating the source and drain of the memory cell during programming.
Yeh teaches floating (Fig. 6: Vs=0/F, Vd=0/F) the source (Fig. 6: 55) and drain (Fig. 6: 56) during a programming operation.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Yeh to the teachings of Noguchi to produce an AND flash memory with a control part that turns the selection gates off during a programming operation in order to float the source and drain of the cell being programmed.
Regarding Claim 17, Noguchi and Kidoh teach the limitations of claim 16. Claim 17 is rejected for the same reasons as claim 13.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (US 20050006696), Kidoh et al (US 20090321813), and Yeh et al (US 20060007732) in view of Nazarian et al (US 20110080792).
Regarding Claim 14, Noguchi, Kidoh and Yeh teaches the limitations of claim 13.
Noguchi further teaches applying a program voltage to the word line of the selected cell (para 87).
However, both fail to teach applying an intermediate voltage to adjacent cells to the selected one during a program operation.
Nazarian teaches applying an intermediate voltage (Fig. 4: MID-VOLTAGE) to adjacent word lines (Fig. 4: WL0, WL2) during a program operation.
It would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to apply the teachings of Nazarian to the teachings of Noguchi and Yeh to produce an AND memory device that applies a programming voltage to selected cells and an intermediate voltage to cells adjacent to the selected cells for the purpose of inducing an additional voltage increase on bitlines to further increase the source/drain voltage of the unselected memory cells to further inhibit them from being programmed (see Nazarian para. 43).
Claims 15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (US 20050006696) and Kidoh et al (US 20090321813) in view of Nazarian et al (US 20110080792).
Regarding Claim 15, Noguchi and Kidoh teaches the limitations of claim 8.
Noguchi is silent to an erasing control part that causes erase of a block all at ones, where the first and second selection transistors are floated and an erase voltage is applied to the channel.
Nazarian further teaches a block erase operation (Fig. 5: BLOCK ERASE OPERATION) where all the cells of the block are erased all at once (para 45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Nazarian’s to the teachings of Noguchi such that Nazarian’s block erase technique is employed in Noguchi’s AND-type memory, for the purpose of performing single erase on the entire block as opposed to erasing unit-by-unit, which would increase the speed of the erase operation of all memory cells.
Regarding Claim 18, Noguchi and Kidoh teach the limitations of claim 16.
Noguchi further teaches applying a program voltage to the word line of the selected cell (para 87).
However, Noguchi fail to teach applying an intermediate voltage to adjacent cells to the selected one during a program operation.
Nazarian teaches applying an intermediate voltage (Fig. 4: MID-VOLTAGE) to adjacent word lines (Fig. 4: WL0, WL2) during a program operation.
It would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to apply the teachings of Nazarian to the teachings of Noguchi to produce an AND memory device that applies a programming voltage to selected cells and an intermediate voltage to cells adjacent to the selected cells for the purpose of inducing an additional voltage increase on bitlines to further increase the source/drain voltage of the unselected memory cells to further inhibit them from being programmed (see Nazarian para. 43).
Regarding Claim 20, Noguchi and Kidoh teach the limitations of Claim 19. Claim 20 is rejected for the same reasons as claim 15.
Response to Arguments
Applicant's arguments filed January 23, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments primarily deal with the addition of the limitation to claims 1, 16 and 19 that memory cells include shallow trench isolations which separated adjacent cells in the row directions but not in the column direction. As the trenches run in the shallow direction. Applicant contends that Noguchi fails to teach this structure pointing to figure 14 in that reference and the lack of shallow trench isolation structures present. However, figure 20 of Noguchi shows structures (element 64) analogous to shallow trench Isolation structures separating memory cells in the row direction. Though the structure is not specifically referred to as a “shallow trench isolation” it is understood to be an isolation structure from its description in paragraph 178 of Noguchi. Thus the claim that Noguchi fails to anticipate this limitation is not persuasive.
Further Applicant states that because Kidoh fails to teach that the charge storage layer is separated in the row direction and shared in the column direction by cells because the continuous charge layer is in continuous in the “z direction.” The z direction is understood to be an arbitrary special axis as part of a coordinate system. It does not refer specifically to any part of a memory array and only exists in relation to other arbitrarily defined axes, typically an x axis and y axis. In relation to a semiconductor device, it is commonly used to describe the direction of structures extending vertically from the substrate. It does not however describe specific orientations within a memory array, like column or row direction describe. Specifically. the column direction is used to describe cells that share a common bit line and different word lines. And the Row direction is used to describe cells that share a common word line and different bit lines. In the case of Kidoh the “z direction” and column direction are understood to be the same. All the cells in the vertical column share a common bit line and the charge layer is shared among adjacent cells that all have different word lines. Thus the argument that the “z direction” represents a different structural feature to the column direction disclosed by applicant is not persuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825