DETAILED ACTION
This action is responsive to the application No. 18/454,105 filed on August 23, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 03/05/2026 responding to the Office action mailed on 12/19/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Claims 6-11, 13, 18, and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 12, 14-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2024/0014314 in view of Kim (US 2023/0290848).
Regarding Claim 1, Tsai (see, e.g., Figs. 1A-1E), teaches an integrated circuit device comprising:
a substrate 10 (see, e.g., par. 0040);
a word line 12e1/12e2 that is in the substrate 10 and extends longitudinally in a first horizontal direction (see, e.g., par. 0071);
a gate dielectric film 12d extending between the substrate 10 and the word line 12e1/12e2 (see, e.g., par. 0061); and
an insulating capping pattern 12c that is in the substrate 10 and on the word line 12e1/12e2, the insulating capping pattern 12c extending longitudinally in the first horizontal direction (see, e.g., pars. 0061, 0077),
wherein the word line 12e1/12e2 comprises a work-function control conductive plug 12e2 that comprises a conductive metal nitride (see, e.g., par. 0069), and
the work-function control conductive plug 12e2 comprises a top surface in contact with a bottom surface of the insulating capping pattern 12c, a sidewall in contact with the gate dielectric film 12d and a bottom surface in contact with a monolithic layer 12e1,
wherein:
the word line 12e1/12e2 further comprises a first conductive plug 12e1 that is spaced apart from the insulating capping pattern 12c in a vertical direction with the work-function control conductive plug 12e2 therebetween, the first conductive plug 12e1 comprises a bottom surface and a sidewall that are both in contact with the gate dielectric film 120.
Tsai is silent with respect to the claim limitation that the conductive metal nitride comprises a metal dopant.
Kim (see, e.g., Fig. 2A), in similar semiconductor devices to Tsai, on the other hand, teaches that by doping the third gate electrode 111 horizontally overlapping with the first and second source/drain regions 113 and 114 with a low work function adjusting element, the gate induced drain leakage (GIDL) can be improved (see, e.g., pars. 0021, 0038-0039, 0046).
It would have been obvious to one of ordinary skill in the art at the time of filing to dope the conductive metal nitride of Tsai’s device with a metal, as taught by Kim, to lower the work function and improve the gate induced drain leakage (GIDL).
Regarding Claim 2, Tsai and Kim teach all aspects of claim 1. Tsai (see, e.g., Figs. 1A-1E), teaches that:
the first conductive plug 12e1 comprises an undoped conductive metal nitride (i.e., TiN, TaN, WV), and the first conductive plug 12e1 comprises a top surface in contact with the bottom surface of the work-function control conductive plug 12e2 (see, e.g., par. 0066), and
a work function of the work-function control conductive plug 12e2 is smaller than a work function of the first conductive plug 12e1 (see, e.g., par. 0072).
Regarding Claim 3, Tsai and Kim teach all aspects of claim 1. Tsai (see, e.g., Figs. 1A-1E), teaches that:
the sidewall of the work-function control conductive plug 12e2 and the sidewall of the first conductive plug 12e1 are on the same plane without a step adjacent to an interface between the work-function control conductive plug 12e2 and the first conductive plug 12e1,
the work-function control conductive plug 12e2 comprises TiN (see, e.g., par. 0069), and
the first conductive plug 12e1 comprises undoped TiN (see, e.g., par. 0066).
Kim (see, e.g., Fig. 2A), in similar semiconductor devices to Tsai, on the other hand, teaches that the work function control conductive plug 111 comprises TiN that comprises lanthanum (La) as a dopant, to lower the work function and improve the gate induced drain leakage (GIDL) (see, e.g., pars. 0021, 0038-0039, 0046).
Regarding Claim 4, Tsai and Kim teach all aspects of claim 1. Tsai (see, e.g., Figs. 1A-1E), teaches that:
the first conductive plug 12e1 comprises a first top surface in contact with the bottom surface of the work-function control conductive plug 12e2, and
the first conductive plug 12e1 further comprises first surfaces (i.e., left and right surfaces of 12e1) that are different from the first top surface and are in contact with the gate dielectric film 12d.
Regarding Claim 5, Tsai and Kim teach all aspects of claim 1. Tsai (see, e.g., Figs. 1A-1E), teaches that:
the substrate 10 comprises a plurality of active regions 10a defined by a device isolation film 10i (see, e.g., par. 0040),
the word line 12e1/12e2 and the insulating capping pattern 12c each have a line shape and intersect with the plurality of active regions 10a and the device isolation film 10i,
the first conductive plug 12e1 is enclosed by the work-function control conductive plug 12e2 and the gate dielectric film 12d, and
the first conductive plug 12e1 comprises a portion that vertically overlaps one of the plurality of active regions 10a and has a first length in the vertical direction and a portion 11e1 that vertically overlaps the device isolation film 10i and has a second length in the vertical direction, and the first length is shorter than the second length (see, e.g., Fig. 1B).
Regarding Claim 12, Tsai and Kim teach all aspects of claim 1. Tsai (see, e.g., Figs. 1A-1E), teaches that the work-function control conductive plug 12e2 comprises TiN (see, e.g., par. 0069), the first conductive plug 12e1 comprises undoped TiN (see, e.g., par. 0066).
Kim (see, e.g., Fig. 2A), in similar semiconductor devices to Tsai, on the other hand, teaches that the work function control conductive plug 111 comprises TiN that comprises lanthanum (La) as a dopant, to lower the work function and improve the gate induced drain leakage (GIDL) (see, e.g., pars. 0021, 0038-0039, 0046).
Regarding Claim 14, Tsai (see, e.g., Figs. 1A-1E), teaches an integrated circuit device comprising:
a substrate 10 comprising a plurality of active regions 10a and a word line trench 10t1/10t2, the plurality of active regions 10a being defined by a device isolation film 10i, and the word line trench 10t1/10t2 extending longitudinally in a first horizontal direction across the plurality of active regions 10a (see, e.g., pars. 0040, 0042);
a gate dielectric film 11d/12d in contact with the plurality of active regions 10a and the device isolation film 10i inside the word line trench 10t1 (see, e.g., pars. 0061, 0078);
a word line 12e1/12e2 in a lower portion of the word line trench 10t2 on the gate dielectric film 12d, the word line 12e1/12e2 extending longitudinally in the first horizontal direction (see, e.g., par. 0061);
an insulating capping pattern 12c in an upper portion of the word line trench 10t2 on the word line 12e1/12e2, the insulating capping pattern 12c extending longitudinally in the first horizontal direction (see, e.g., par. 0061); and
a pair of source/drain regions 101/102 on respective sides of the word line 12e1/12e2 in one of the plurality of active regions 10a (see, e.g., par. 0041), wherein the word line 12e1/12e2 comprises:
a work-function control conductive plug 12e2 that comprises a conductive metal nitride, the work-function control conductive plug 12e2 comprising a gate top surface in contact with the insulating capping pattern 12c and a pair of upper sidewalls (i.e., left and right sidewalls) in contact with the gate dielectric film 12d, the pair of upper sidewalls facing the pair of source/drain regions 101/102, respectively, and the work-function control conductive plug 12e2 extending continuously in a second horizontal direction between the pair of upper sidewalls, wherein the second horizontal direction is perpendicular to the first horizontal direction (see, e.g., par. 0069); and
a first conductive plug 12e1 comprising an undoped conductive metal nitride, the first conductive plug 12e1 comprising a bottom surface and a sidewall that are both in contact with the gate dielectric film 12d (see, e.g., par. 0066).
Tsai is silent with respect to the claim limitation that the work-function control conductive plug 12e2 comprises a conductive metal nitride comprising a metal dopant.
Kim (see, e.g., Fig. 2A), in similar semiconductor devices to Tsai, on the other hand, teaches that by doping the third gate electrode 111 horizontally overlapping with the first and second source/drain regions 113 and 114 with a low work function adjusting element, the gate induced drain leakage (GIDL) can be improved (see, e.g., pars. 0021, 0038-0039, 0046).
It would have been obvious to one of ordinary skill in the art at the time of filing to dope the conductive metal nitride of Tsai’s device with a metal, as taught by Kim, to lower the work function and improve the gate induced drain leakage (GIDL).
Regarding Claim 15, Tsai and Kim teach all aspects of claim 14. Tsai (see, e.g., Figs. 1A-1E), teaches that a work function of the work-function control conductive plug 12e2 is less than a work function of the first conductive plug 12e1 (see, e.g., par. 0072).
Regarding Claim 16, Tsai and Kim teach all aspects of claim 14. Tsai (see, e.g., Figs. 1A-1E), teaches that the first conductive plug 12e1 further comprises first surfaces (i.e., left and right surfaces) that are different from the first top surface and are in contact with the gate dielectric film 12d.
Regarding Claim 19, Tsai (see, e.g., Figs. 1A-1E), teaches an integrated circuit device comprising:
a substrate 10 comprising a word line trench 10t2 that extends longitudinally in a first horizontal direction (see, e.g., par. 0040, 0042);
a gate dielectric film 12d extending along an inner surface of the word line trench 10t2 (see, e.g., par. 0061);
a word line 12e1/12e2 in a lower portion of the word line trench 10t2 on the gate dielectric film 12d, the word line 12e1/12e2 extending longitudinally in the first horizontal direction (see, e.g., par. 0061); and
an insulating capping pattern 12c in an upper portion of the word line trench 10t2 on the word line 12e1/12e2, the insulating capping pattern 12c extending longitudinally in the first horizontal direction (see, e.g., par. 0061),
wherein the word line 12e1/12e2 comprises:
a titanium nitride (TiN) plug 12e2 comprising a gate top surface in contact with the insulating capping pattern 12c and a pair of upper sidewalls (i.e., left and right sidewalls) in contact with the gate dielectric film 12d, the TiN plug 12e2 extending continuously in a second horizontal direction between the pair of upper sidewalls, wherein the second horizontal direction is perpendicular to the first horizontal direction; and
an undoped TiN plug 12e1 comprising a bottom surface and a sidewall that are bothe in contact with the gate dielectric film 12d (see, e.g., par. 0066),
wherein one of the pair of upper sidewalls and the sidewall of the undoped TiN plug 12e1 are on the same plane without a step adjacent to an interface between the TiN plug 12e2 and the undoped TiN plug 12e1 (see, e.g., Fig. 1B).
Tsai is silent with respect to the claim limitation that the TiN plug 12e2 comprises a lanthanum as a dopant.
Kim (see, e.g., Fig. 2A), in similar semiconductor devices to Tsai, on the other hand, teaches that by doping the titanium nitride (TiN) plug 12e2 with lanthanum, the gate induced drain leakage (GIDL) can be improved (see, e.g., pars. 0021, 0038-0039, 0046).
It would have been obvious to one of ordinary skill in the art at the time of filing to dope the TiN plug of Tsai’s device with lanthanum, as taught by Kim, to lower the work function and improve the gate induced drain leakage (GIDL).
Response to Arguments
Applicant’s arguments with respect to the rejection of claims 1, 14, and 19 filed on 03/05/2026 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
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/Nelson Garces/
Primary Examiner, Art Unit 2814