DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 08/23/2023 has been acknowledged and a signed copy of the PTO-1449 is attached herein.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (WO 2022067644 A1, however, its equivalent US PG PUB 2022/0302296 A1 is used for the rejection, hereinafter “Zhang”) in view of Cheng et al. (US 2020/0135789 A1, hereinafter “Cheng”).
In regards to claim 1, Zhang discloses (See, for example, Figs. 3) a semiconductor device comprising:
an interlayer insulating film (126); and
a wiring of an uppermost layer (146, and See, for example, Par [0079]) arranged on the interlayer insulating film (126), wherein the wiring includes a seed layer (See, for example, Par [0079]) arranged on the interlayer insulating film (126) and a wiring body portion arranged on the seed layer (See, Par [0079]), and
wherein a trench (224) is formed in an upper surface of the interlayer insulating film along an outer edge of the interlayer insulating film in a plan view (See, Fig. 3D and 3E).
Zhang fails to explicitly teach that wherein a constituent material of the wiring body portion is copper or a copper alloy.
However, Cheng while disclosing a semiconductor device/structure teaches (See, for example, Figs. 1 and 7) a constituent material of the wiring body portion (See, for example, 315/317, 415/417) is copper or a copper alloy (See, for example, Pars [0026] and [0032]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate copper or copper alloy for the material of the wiring body of Cheng to Zhang because this would help improve the performance and reliability of the semiconductor device.
In regards to claim 6, Zhang discloses (See, for example, Figs. 3) a method of manufacturing a semiconductor device, comprising:
forming an interlayer insulating film (126);
forming a via hole (140) in the interlayer insulating film (126);
embedding a via plug in the via hole (See, for example, 212, 140, and Fig. 3B);
forming a wiring of an uppermost layer on the interlayer insulating film (See, for example, Par [0079]); and
forming a trench (224) in an upper surface of the interlayer insulating film (126),
wherein the wiring is formed by forming a seed layer on the interlayer insulating film (See, for example, Par [0079]),
forming a first resist (240) pattern having a first opening on the seed layer (146),
forming a wiring body portion on the seed layer exposed through the first opening by performing electroplating (See, for example, Par [0079]), and
removing the seed layer by etching using the wiring body portion as a mask (See, for example, Fig. 3I and 3J);
wherein the interlayer insulating film (126) is located above a semiconductor substrate (102), wherein the semiconductor substrate (102) includes, in a plan view, a plurality of element forming regions (204) and a scribe region between two adjacent ones of the plurality of element forming regions, and wherein the trench (224) is formed so as to overlap the scribe region in a plan view (See, for example, Par [0084]).
Zhang fails to explicitly teach that wherein a constituent material of the wiring body portion is copper or a copper alloy.
However, while disclosing a semiconductor device/structure teaches (See, for example, Figs. 1 and 7) a constituent material of the wiring body portion (See, for example, 315/317, 415/417) is copper or a copper alloy (See, for example, Pars [0026] and [0032]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to incorporate copper or copper alloy for the material of the wiring body of Cheng to Zhang because this would help improve the performance and reliability of the semiconductor device.
In regards to claims 2 and 5, Zhang as modified above discloses all limitations of claim 1 except that the wiring has a thickness of 4 μm or more; and the trench has a depth of 1 μm or more and 6 μm or less.
Notwithstanding, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness range or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. See In re Woodruff, 919, f.2d 1575, 1578, 16 USPQ2d, 1936 (Fed. Cir. 1990).
In regards to claim 4, Zhang as modified above discloses (See, for example, Figs. 3) a via plug (212) electrically connected to the wiring (See, for example, 146 and Par [0079]), wherein a via hole (142, See Fig. 3C) in which the via plug (212) is embedded is formed in the interlayer insulating film (126).
Zhang as modified above is silent about a constituent material of the seed layer is the same as a constituent material of the via plug.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to select the material of the seed layer the same as the material of the via plug, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Cheng as applied to claim 1 above, and further in view of Lee et al. (USPN 6225226 B1, hereinafter “Lee”).
In regards to claim 3, Zhang as modified above discloses (See, for example, Figs. 3) a via plug (See, for example, 212, Figs. 3B and 3C) electrically connected to the wiring (See, for example, 146 and Par [0079]), wherein a via hole (142, See, Fig. 3C) in which the via plug (212, See, Fig. 3C) is embedded is formed in the interlayer insulating film (126).
Zhang as modified above further fails to explicitly teach that a constituent material of the seed layer is different from a constituent material of the via plug.
Lee while disclosing copper interconnects teaches (See, for example, Fig. 5) a constituent material of the seed layer (40) is different from a constituent material of the via plug (37).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify Zhang by Lee because this would help reduce the rate of copper migration and avoid shorting.
Allowable Subject Matter
Claims 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 7, The prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach the trench is formed by etching the interlayer insulating film exposed through the third opening using the third resist pattern as a mask.
In regards to claim 8, The prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach a fourth resist pattern having a fourth opening and a fifth opening on the interlayer insulating film, wherein the via hole and the trench are formed by etching the interlayer insulating film exposed through the fourth opening and the interlayer insulating film exposed through the fifth opening, respectively.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893