DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-10, 16-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2022/0246180).
Regarding claim 1, Lee et al. discloses, as shown in Figures 7A-15, a semiconductor memory device comprising:
a bit line (BL) on a substrate (110) and extending in a first direction;
a first active pillar (AP1) and a second active pillar (AP2) on the bit line, the first active pillar comprising a first horizontal portion (HP1)coupled to the bit line and a first vertical portion (VP1) extending from the first horizontal portion in a vertical direction away from the substrate, the second active pillar comprising a second horizontal portion (HP2) coupled to the bit line and a second vertical portion (VP2) extending from the second horizontal portion in the vertical direction;
a first word line (WL1) and a second word line (WL2) on the first and second horizontal portions of the first and second active pillars, respectively, and extending in a second direction crossing the first direction; and
a first insulating layer (141) between the first and second word lines,
wherein a first side surface of the first horizontal portion and a second side surface of the second horizontal portion face each other, and
the first insulating layer comprises a first air gap (AGa) between the first side surface and the second side surface.
Regarding claim 2, Lee et al. discloses the first and second active pillars are symmetric with respect to each other about an axis extending in the vertical direction (Figures).
Regarding claim 3, Lee et al. discloses the first and second active pillars comprise amorphous oxide semiconductor materials, wherein the amorphous oxide semiconductor materials include InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, and/or InGaO [0056].
Regarding claim 4, Lee et al. discloses the memory device further comprising: a third active pillar (W1 or W2) on the bit line; and a second insulating layer (143) between the second active pillar and the third active pillar, wherein the second insulating layer comprises a second air gap (AGb) (Figures 13A-13B).
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Regarding claim 8, Lee et al. discloses the device further comprising:
landing pads (LP) on the first and second vertical portions, respectively; and
data storage patterns (DSP) on the landing pads, respectively (Figures).
Regarding claim 9, Lee et al. discloses each of the data storage patterns comprises a capacitor [0073].
Regarding claim 10, Lee et al. discloses the device further comprising a peripheral circuit structure (PS) including peripheral circuits, which are on the substrate, wherein the peripheral circuit structure is below the bit line (Figures 14 – 15).
Regarding claim 16, Lee et al. discloses, as shown in Figures 7A-15, a semiconductor memory device comprising:
a peripheral circuit structure (PS) including peripheral circuits on a substrate (100);
a bit line (BL) on the peripheral circuit structure and extending in a first direction;
a first active pillar (AP1) and a second active pillar (AP2) on the bit line, the first active pillar comprising a first horizontal portion (HP1) coupled to the bit line and a first vertical portion (VP1) extending from the first horizontal portion in a vertical direction away from the substrate, the second active pillar comprising a second horizontal portion (HP2) coupled to the bit line and a second vertical portion (VP2) extending from the second horizontal portion in the vertical direction;
a first word line (WL1) and a second word line (WL2) on the first and second horizontal portions of the first and second active pillars, respectively, and extending in a second direction crossing the first direction;
a first gate insulating layer (Gox1) between the first active pillar and the first word line and a second gate insulating layer (Gox2) between the second active pillar and the second word line;
a first insulating layer (141) between the first and second word lines;
a gate capping pattern (170) on top surfaces of the first and second word lines and a top surface of the first insulating layer;
landing pads (LP) on the first and second active pillars, respectively; and
a plurality of data storage patterns (DSP) on the landing pads, respectively,
wherein the first insulating layer comprises at least one air gap (AGa).
Regarding claim 17, Lee et al. discloses a first side surface of the first horizontal portion and a second side surface of the second horizontal portion face each other with the first insulating layer therebetween, and the at least one air gap comprises a first air gap between the first side surface and the second side surface (Figures 13A-13B).
Regarding claim 19, Lee et al. discloses the first side surface is vertically aligned to a side surface of the first word line, and the second side surface is vertically aligned to a side surface of the second word line (Figures).
Regarding claim 20, Lee et al. discloses the first and second active pillars comprise amorphous oxide semiconductor materials, wherein the amorphous oxide semiconductor materials include InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, and/or InGaO [0056].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7, 11-15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0246180).
Regarding claim 5, Lee et al. does not disclose a first distance between the first and second word lines is smaller than a second distance between the second active pillar and the third active pillar. However, in a different embodiment of Figure 5, Lee et al. a first distance between the first and second word lines is smaller than a second distance between the second active pillar and the third active pillar. Therefore, it would be have been obvious to one of ordinary skills in the art at the time the invention was made to modify the a first distance between the first and second word lines of Lee et al. being smaller than a second distance between the second active pillar and the third active pillar, such as taught by Figure 5 of Lee et al. in order to have the desired patterned structure.
Regarding claims 6-7 and 18, Lee et al. does not disclose the second air gap is positioned to be higher than the first air gap relative to the substrate, nor the second air gap is larger than the first air gap. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, height, dimension, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, height, dimension, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claims 11 and 13, Lee et al. discloses, as shown in Figures 7A-15, a semiconductor memory device comprising:
a bit line (BL) on a substrate (100,110) and extending in a first direction;
first active pillars (AP1) and second active pillars (AP2) on the bit line, the first and second active pillars being alternately arranged in the first direction, each of the first and second active pillars comprising a horizontal portion (HP1,HP2) coupled to the bit line and a vertical portion (VP1,VP2) extending from the horizontal portion in a vertical direction away from the substrate;
first word lines (W1) on the horizontal portions of the first active pillars, respectively;
second word lines (W2) on the horizontal portions of the second active pillars, respectively, the first and second word lines being extending in a second direction crossing the first direction;
a first insulating layer (141) between the first word line and the second word line, which are adjacent to each other; and
a second insulating layer (143) between the vertical portion of the first active pillar and the vertical portion of the second active pillar, which are adjacent to each other,
wherein the first insulating layer comprises a first air gap (AGa),
the second insulating layer comprises a second air gap (AGb).
Lee et al. does not disclose the second air gap is positioned to be higher than the first air gap relative to the substrate, nor the second air gap is larger than the first air gap. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, height, dimension, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, height, dimension, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 12, Lee et al. discloses the first air gap is between the horizontal portions of the first and second active pillars, which face each other (Figures).
Regarding claim 14, Lee et al. discloses further comprising:
landing pads (LP) on the vertical portions of the first and second active pillars, respectively; and
data storage patterns (DSP) on the landing pads, respectively (Figures).
Regarding claim 15, Lee et al. discloses each of the landing pads comprises a portion that is horizontally offset from the vertical portion connected thereto (Figures).
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897