Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-11, 14-18, 20-21, 24-26, 29 and 32-34 are rejected under 35 U.S.C. 103 as being unpatentable over Liff(US20200098692A1) in view of Kuroda et al (US 2010/0078635 A1).
With respect to Claim 1, Fig. 7A displays, a semiconductor package assembly, comprising:
a first semiconductor die (Fig7A; 104; ¶ [0061]) and a second semiconductor die (Fig 7A; 114-1; ¶ [0061]) stacked on each other (Fig 7A; 104-first and 114-1-second), wherein the first semiconductor die comprises:
a first interface (see Fig. 7A schematic annotation-first interface) overlapping and electrically connected to a second interface (see Fig. 7A schematic annotation-second interface) arranged on the second semiconductor die; and
a third interface arranged on a first edge of the first semiconductor die (see Fig. 7A schematic annotation-second interface); and
a memory package (Fig. 7A; 114-2; ¶ [0061]; ¶ [0034]; on-package memory devices) beside the first semiconductor die (Fig. 7A; 104; ¶ [0061]), wherein the memory package is electrically connected to the first semiconductor die by the third interface (see Fig. 7A schematic annotation-third interface).
Liff does not explicitly disclose each of the first semiconductor die, the second semiconductor die and the memory package comprises a pair of opposite edges, and the pair of opposite edges of the first semiconductor die, the pair of opposite edges of the second semiconductor die and the pair of opposite edges of the memory package are corresponding to and parallel to each other in a top view.
However, Kuroda discloses each of the first semiconductor die 210 (Figs. 2, 8, Para. 131), the second semiconductor die 200 (Para. 131) and the memory package 201 (Para. 131) comprises a pair of opposite edges, and the pair of opposite edges of the first semiconductor die 210, the pair of opposite edges of the second semiconductor die 200 and the pair of opposite edges of the memory package 201 are corresponding to and parallel to each other in a top view (Fig. 2). Kuroda teaches the above modification is used to control memory of the device (Para. 131). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Liff structure with Kuroda chip arrangements as suggested above to control memory of the device (Para. 131).
With respect to Claim 2, Fig. 7A displays, the semiconductor package assembly as claimed in Claim 1, wherein the first semiconductor die has a first critical dimension (Fig 7A; 104; narrower) and the second semiconductor die has a second critical dimension (Fig 7A; 114-1; wider), wherein the first critical dimension is narrower than the second critical dimension.
With respect to Claim 8, Fig. 7A displays, the semiconductor package assembly as claimed in Claim 1, wherein the second semiconductor die and the memory package are arranged side-by-side along a first direction (Fig 7A; 114-1 second die and 114-2 memory package), and wherein the second semiconductor die and the memory package are stacked on the first semiconductor die along a second direction that is different from the first direction (Fig 7A; 104 first die, 114-1 second die and 114-2 memory package).
With respect to Claim 9, Fig. 7A discloses the semiconductor package assembly as claimed in Claim 8, wherein the third interface is arranged overlapping the memory package along the second direction, and the third interface is arranged on three adjacent edges of the first semiconductor die (Fig. 7A; 117-2; ¶ [0025]; see Fig. 7A schematic and annotation-third interface).
With respect to Claim 10, Fig. 7A displays, the semiconductor package assembly as claimed in Claim 8, wherein the first interface is arranged on a third edge of the first semiconductor die and opposite the first edge (see Fig 7A schematic and annotation-first interface; third edge and first edge).
With respect to Claim 11, Fig. 7A displays, the semiconductor package assembly as claimed in Claim 8, wherein the first semiconductor die comprises: third through via (TV) interconnects disposed within the third interface and electrically connected to the memory package (Fig 7A; 130; ¶ [0062]); and (see Fig. 7A schematic and annotations-third interface)
fourth TV interconnects disposed within the first interface and electrically connected to the second interface of the second semiconductor die (Fig 7A; 130; ¶ [0062]). (see Fig. 7A schematic and annotations-first interface)
With respect to Claim 14, ¶ [0030] discloses, teaches the semiconductor package assembly as claimed in Claim 8, wherein the first semiconductor die comprises a trench capacitor embedded within the third interface and electrically connected to the memory package (¶ [0030]; the capacitor is included in die 104 and the third interface is on the first edge of 104 which is electrically connected to the memory package).
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Fig. 7A schematic with annotations for Claims 1, 2, 8, 9, 10, 11, and 14
*Annotations overlay features described in specifications and displayed in figure
With respect to Claim 15, The semiconductor package assembly as claimed in Claim 1, further comprising:
a fan-out package comprising the first semiconductor die (Fig7A; 104; ¶ [0061]), the second semiconductor die (Fig 7A; 114-1; ¶ [0061]) and the memory package (Fig. 7A; 114-2; ¶ [0061]), wherein the fan-out package further comprises:
a first redistribution layer (RDL) structure (see Fig 7A schematic annotation-RDL1) disposed between the first semiconductor die (Fig7A; 104; ¶ [0061]) and the second semiconductor die (Fig 7A; 114-1; ¶ [0061]), wherein the first RDL structure (see Fig 7A schematic annotation-RDL1) is electrically connected to the first interface, the second interface, the third interface and the memory package (see Fig 7A schematic annotation-RDL1, first interface, second interface and third interface);
a second redistribution layer (RDL) (see Fig 7A schematic annotation-RDL2) structure electrically connected to the first RDL structure and separated from the memory package by the first RDL structure (see Fig 7A schematic annotation-RDL2, RDL1 and memory package);
a first molding compound covering the first RDL structure and the memory package (Fig. 1B; 103-2; ¶ [0061] dielectric layers);
a second molding compound filling a space between the first RDL structure and the second RDL structure (Fig. 1B; 103-1; ¶ [0061] dielectric layers);
a fifth TV interconnect (Fig. 7A; 151; ¶ [0061]) passing through the second molding compound and electrically connected to the first RDL (see Fig 7A schematic annotation-RDL1) structure and the second RDL structure (see Fig 7A schematic annotation-RDL2); and
second conductive structures in contact with and electrically connected to the second RDL structure (Fig. 7A; 146; ¶ [0029]; see Fig 7A schematic annotation-RDL2).
With respect to Claim 16, the semiconductor package assembly as claimed in Claim 15, wherein the first semiconductor die comprises a fifth interface arranged adjacent to the third interface (see Fig 7A schematic annotation-fifth interface).
With respect to Claim 17, The semiconductor package assembly as claimed in Claim 16, wherein the fifth interface (see Fig 7A schematic annotation-fifth interface) is electrically connected to the second conductive (Fig. 7A; 146; ¶ [0061]) structures outside the first edge by the second RDL structure (see Fig 7A schematic annotation- RDL2) rather than the first RDL structure.
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Fig. 7A schematic with annotations for Claims 15-17
*Annotations overlay features described in specifications and displayed in figure
With respect to Claim 18, A semiconductor package assembly, comprising: a fan-out package, comprising: a memory package (Fig. 7A; 114-2; ¶ [0061]);
a first semiconductor die direction (Fig. 7A; 104; ¶ [0061]) arranged beside the memory package along a first direction (Fig. 7A; 114-2; ¶ [0061]); and
a second semiconductor die arranged beside the memory package along a second direction (Fig. 7A; 114-1; ¶ [0061]), wherein the first semiconductor die comprises: a first interface (see Fig. 7A schematic annotation-first interface) overlapping and electrically connected to a second interface (see Fig. 7A schematic annotation-second interface) arranged on the second semiconductor die; and
a third interface (see Fig. 7A schematic annotation-third interface) arranged close to and electrically connected to the memory package.
Liff does not explicitly disclose each of the first semiconductor die, the second semiconductor die and the memory package comprises a pair of opposite edges, and the pair of opposite edges of the first semiconductor die, the pair of opposite edges of the second semiconductor die and the pair of opposite edges of the memory package are corresponding to and parallel to each other in a top view.
However, Kuroda discloses each of the first semiconductor die 210 (Figs. 2, 8, Para. 131), the second semiconductor die 200 (Para. 131) and the memory package 201 (Para. 131) comprises a pair of opposite edges, and the pair of opposite edges of the first semiconductor die 210, the pair of opposite edges of the second semiconductor die 200 and the pair of opposite edges of the memory package 201 are corresponding to and parallel to each other in a top view (Fig. 2). Kuroda teaches the above modification is used to control memory of the device (Para. 131). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Liff structure with Kuroda chip arrangements as suggested above to control memory of the device (Para. 131).
With respect to Claim 20, The semiconductor package assembly as claimed in Claim 18, further comprising:
a first redistribution layer (RDL) structure (¶ [0061]; see Fig. 7A schematic annotation-RDL1) disposed between the first semiconductor die (Fig. 7A; 104; ¶ [0061]) and the second semiconductor die (Fig. 7A; 114-1; ¶ [0061]), wherein the first RDL structure (see Fig. 7A schematic annotation-RDL1) is electrically connected to the first interface, the second interface, the third interface and the memory package; and (see Fig. 7A schematic with annotations-RDL1, first interface, second interface, third interface and memory package)
a second redistribution layer (RDL) structure (¶ [0061]; see Fig. 7A illustration with annotations-RDL2) electrically connected to the first RDL structure and separated from the memory package by the first RDL structure. (see Fig. 7A schematic with annotations-RDL1 and memory package)
With respect to Claim 21, The semiconductor package assembly as claimed in Claim 20, wherein the first semiconductor die is disposed between the first RDL structure and the second RDL structure (see Fig. 7A schematic with annotations-114-1, RDL1 and RDL2) and comprises through via (TV) interconnects disposed within the first interface and the third interface (130; Fig. 7A; ¶ [0061])
With respect to Claim 24, The semiconductor package assembly as claimed in Claim 21, wherein the first semiconductor die comprises a fifth interface (see Fig. 7A schematic with annotations-fifth interface) arranged adjacent to the third interface (see Fig. 7A schematic with annotations-third interface) and on a first edge (see Fig. 7A schematic with annotations-first edge) of the first semiconductor die, so that the third interface is arranged between the first interface and the fifth interface along the second direction(see Fig. 7A schematic with annotations-first interface and fifth interface).
With respect to Claim 25, The semiconductor package assembly as claimed in Claim 24, wherein the fifth interface structure (see Fig. 7A schematic with annotations-fifth interface) is electrically connected to second conductive structures (Fig. 7A; 146; ¶ [0059]) in contact with and electrically connected to the second RDL structure (see Fig. 7A schematic with annotation-RDL2) and outside the first edge by the second RDL structure rather than the first RDL structure.
With respect to Claim 26, The semiconductor package assembly as claimed in Claim 21, wherein the first semiconductor die comprises a trench capacitor embedded within the third interface and electrically connected to the memory package by the first RDL structure (¶ [0030]; the capacitor is included in die 104 and the third interface is on the first edge of 104 which is electrically connected to the memory package).
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Fig. 7A schematic with annotations for Claims 18, 20, 21, 24, 25 and 26
*Annotations overlay features described in specifications and displayed in figure
With respect to Claim 29, Fig. 1B displays, a semiconductor package assembly, comprising: a fan-out package, comprising: a first redistribution layer (RDL) structure (Fig. 1B; ¶ [0061]; see Fig. 1B schematic-RDL1) and a second redistribution layer (RDL) structure (Fig. 1B; ¶ [0061]; see Fig. B1 schematic-RDL2) stacked on each other;
a top semiconductor die (Fig. 1B; 114-1; ¶ [0025]) and a memory package (Fig. 1B; 114-2; ¶ [0025]) disposed on the first redistribution layer (RDL) structure (Fig 1B; ¶ [0061]; see Fig. 1B schematic annotation-RDL1), wherein the top semiconductor die comprises a first interface (see Fig. 1B schematic annotation-first interface); and
a bottom semiconductor die disposed between the first RDL structure and the second RDL structure (Fig. 1B, 104; see Fig. 1B schematic annotation- RDL1 and RDL2) wherein the bottom semiconductor die comprises: a second interface overlapping the first interface (Fig. 1B; 191; ¶ [0033]; see Fig. 1B schematic annotation-first interface and second interface); and
first through via (TV) interconnects arranged within the second interface and electrically connected to the first interface by the first RDL structure (Fig. 1B; 130; ¶ [0026]; see Fig. 1B schematic annotation-RDL1), and wherein the memory package is electrically connected to the top semiconductor die and the bottom semiconductor die by the first RDL structure rather than the second RDL structure (Fig. 1B; 114-2; ¶ [0061] see Fig. 1B schematic annotation-RDL1).
Liff does not explicitly disclose each of the top semiconductor die, the bottom semiconductor die and the memory package comprises a pair of opposite edges, and the pair of opposite edges of the top semiconductor die, the pair of opposite edges of the bottom semiconductor die and the pair of opposite edges of the memory package are corresponding to and parallel to each other in a top view.
However, Kuroda discloses each of the top semiconductor die 210 (Figs. 2, 8, Para. 131), the bottom semiconductor die 200 (Para. 131) and the memory package 201 (Para. 131) comprises a pair of opposite edges, and the pair of opposite edges of the top semiconductor die 210, the pair of opposite edges of the bottom semiconductor die 200 and the pair of opposite edges of the memory package 201 are corresponding to and parallel to each other in a top view (Fig. 2). Kuroda teaches the above modification is used to control memory of the device (Para. 131). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Liff structure with Kuroda chip arrangements as suggested above to control memory of the device (Para. 131).
With respect to Claim 32, Fig. 1B displays, the semiconductor package assembly as claimed in Claim 29, wherein the bottom semiconductor die comprises a fourth interface overlapping the memory package (Fig. 1B; 117-2; ¶ [0025]; see Fig. 1B schematic annotation-fourth interface), wherein the memory package (Fig. 1B; 114-2; ¶ [0025]) is electrically connected to the bottom semiconductor die (Fig. 1B; 104; ¶ [0025]) by the fourth interface.
With respect to Claim 33, Fig. 1B displays, the semiconductor package assembly as claimed in Claim 32, wherein the bottom semiconductor die comprises a fifth interface (see Fig. 1B schematic annotation-fifth interface) arranged adjacent to the fourth interface (see Fig. 1B schematic annotation-fourth interface) and on a first edge of the bottom semiconductor die, so that the fourth interface is disposed between the second interface (see Fig. 1B schematic annotation-second interface) and the fifth interface.
With respect to Claim 34, Fig. 1B displays, the semiconductor package assembly as claimed in Claim 32, wherein the bottom semiconductor die comprises third through via (TV) interconnects (Fig. 1B; 130; ¶ [0026]) arranged within the fourth interface (see Fig. 1B schematic annotation-fourth interface and electrically connected to the memory package (Fig. 1B; 114-2; ¶ [0025])
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Fig. 1B schematic with annotations for Claims 29, 32, 33 and 34
*Annotations overlay features described in specifications and displayed in figure
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Liff(US20200098692A1) in view of Kuroda et al (US 2010/0078635 A1) and further in view of Choi(US20230215849A1).
With respect to Claim 36, Liff teaches the semiconductor package assembly as claimed in Claim 29, wherein the bottom semiconductor die comprises a trench capacitor embedded in the bottom semiconductor die (¶ [0030]) and
the memory package (Fig 7A; 114-2; ¶ [0061]).
Liff does not teach electrically connected.
Choi teaches capacitor electrically connected (Fig. 1A; 130; ¶ [0037]).
It would be obvious to one with ordinary skill in the art before the effective filing date to combine the invention of Liff, a semiconductor package with a capacitor included in the bottom die, and the invention of Choi, a semiconductor package with a deep trench capacitor embedded on a substrate and coupled to a semiconductor die. This combination would produce a semiconductor package with a trench capacitor embedded on the bottom die and in contact with a neighboring die which is the memory package of Liff(114-2). The trench capacitor provides a decoupling capacitance to shunt noise Choi(¶ [0037]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 8-11, 14-18, 20-21, 24-26, 29 and 32-34, 36 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Yee(US20170062383A1); This refence teaches a semiconductor packaging method with two semiconductor dies placed over a substrate
Li(US20220271002A1); This refence teaches a semiconductor packaging method of a three die construction
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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