Prosecution Insights
Last updated: April 19, 2026
Application No. 18/454,242

DYNAMIC PLATED METAL THICKNESS FOR SEMICONDUCTOR PACKAGE

Non-Final OA §103
Filed
Aug 23, 2023
Examiner
GEBREMARIAM, SAMUEL A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
685 granted / 825 resolved
+15.0% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
19 currently pending
Career history
844
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
36.5%
-3.5% vs TC avg
§102
31.3%
-8.7% vs TC avg
§112
21.2%
-18.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 825 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claim 1-7 in the reply filed on 12/01/2025 is acknowledged. Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kubara et al., US 2002/0053721. Regarding claim 1, Kubara discloses (fig. 3 and related text) a semiconductor package, comprising: a semiconductor component (9); a plurality of leads (2) electrically connected to the semiconductor component (via 10); an encapsulation material (10) contacting the semiconductor component (9) and the leads (2), wherein the leads extend through the encapsulation material (11) to an exterior of the semiconductor package (fig. 3), each of the leads (2) having a first surface and a second surface opposite from the first surface (fig. 3); and a solderable metal on the leads (7). Kubara does not explicitly disclose the solderable metal having a first average thickness on the first surfaces and having a second average thickness on the second surfaces, wherein the second average thickness is 10 percent to 80 percent of the first average thickness. Parameters such as average thickness in the art of semiconductor process are subject to routine experimentation and optimization to achieve the desired device characterization during fabrication. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize an appropriate average thickness to meet the requirements of the particular design, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233. Regarding claim 2, Kubara as modified discloses the solderable metal primarily includes a metal selected from the group consisting of tin, silver, and an alloy thereof [0077]. Regarding claim 3, Kubara as modified discloses wherein the solderable metal primarily includes tin ([0077]). Regarding claim 4, Kubara does not explicitly disclose the first average thickness of the solderable metal is 5 microns to 20 microns. Parameters such as average thickness in the art of semiconductor process are subject to routine experimentation and optimization to achieve the desired device characterization during fabrication. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize an appropriate average thickness to meet the requirements of the particular design, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. /n re Aller, 105 USPQ 233. Regarding claim 5, Kubara as modified discloses the leads (2) have a gull wing configuration (fig. 3). Regarding claim 7, Kubara as modified discloses the solderable metal (7) exposes a portion of the leads (2) adjacent to the semiconductor component (9, fig. 3). Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kubara in view of Harden et al., US 2003/0062601. Regarding claim 6, Kubara as modified does not disclose the leads have a j-lead configuration. Harden discloses a j-lead configuration(fig. 6A and related text) in order to allow maximum space efficiency to the package [0174]. Kubara and Harden are analogous art because they both are directed to semiconductor package with leadframe and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen with the specified features of Lee because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, on the effective filing date of the claimed invention, to modify Kubara to include the j-lead configuration as taught by Harden in order to allow maximum space efficiency to the package [0174]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Aug 23, 2023
Application Filed
Dec 27, 2025
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+8.9%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 825 resolved cases by this examiner. Grant probability derived from career allow rate.

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