DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on March 24, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 6-7, 9-11, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0025944 A1 to Lee et al. (“Lee”) in view of U.S. Patent Application Publication No. 2013/0208473 A1 to Palagashvili et al. (“Palagashvili”). As to claim 1, Lee in view of Palagashvili discloses a power semiconductor device, comprising: a molded package comprising one or more power semiconductor dies (11, 17/17) embedded in a mold compound (13, 14) and forming part of a power electronics circuit (11, 17/17), wherein a metallic region (15, 16) exposed at a topside of the molded package forms part of a primary thermal pathway for heat dissipated by the one or more power semiconductor dies (11, 17/17) during operation; and an insulated metal substrate (IMS) (20) comprising a copper layer (23) attached to the metallic region (15, 16) exposed at the topside of the molded package, an aluminum layer (21, 30) at an opposite side of the IMS (20) as the copper layer (23), and an organic isolation layer (22) that electrically isolates the copper layer (23) and the aluminum layer (21, 30) from one another, wherein the copper layer (23) provides no electrical rerouting for the molded package (See Lee Fig. 2, Fig. 3, ¶ 0027-¶ 0035 and Palagashvili Fig. 1, ¶ 0032, ¶ 0036) (Notes: the copper layer is insulated by the organic isolation layer such that no rerouting to the aluminum layer is provided, which is the same as shown in FIG. 1 of the Application and as the recited elements. Further, having the power semiconductor dies to supply power and drive the LED chip is well-known in the art). As to claim 4, Lee further discloses wherein the molded package is a surface mount package (See Fig. 2, Fig. 3, ¶ 0032). As to claim 6, Lee discloses further comprising a thermal interface material (40) applied to the aluminum layer (21, 30) of the IMS (20) (See Fig. 2, ¶ 0033). As to claim 7, Lee further discloses wherein the aluminum layer (21, 30) of the IMS (20) is thicker than the thermal interface material (40) (See Fig. 2). As to claim 9, Lee further discloses wherein the copper layer (23) of the IMS (20) is glued, soldered, or welded to the metallic region (15, 16) exposed at the topside of the molded package (See Fig. 2) (Notes: the physical attachment is glued). As to claim 10, Lee in view of Palagashvili discloses a power electronics assembly, comprising: a circuit board (12 module, communication substrate); a plurality of power semiconductor devices (11, 17/17) mounted to the circuit board (12 module, communication substrate) and each comprising: a molded package comprising one or more power semiconductor dies (11, 17/17) embedded in a mold compound (13, 14) and forming part of a power electronics circuit (11, 17/17), wherein a metallic region (15, 16) exposed at a side of the molded package that faces away from the circuit board (12 module, communication substrate) forms part of a primary thermal pathway for heat dissipated by the one or more power semiconductor dies (11, 17/17) during operation; and an insulated metal substrate (IMS) (20) comprising a copper layer (23) attached to the metallic region (15, 16) exposed at the side of the molded package that faces away from the circuit board (12 module, communication substrate), an aluminum layer (21, 30) at an opposite side of the IMS (20) as the copper layer (23), and an organic isolation layer (22) that electrically isolates the copper layer (23) and the aluminum layer (21, 30) from one another, wherein the copper layer (23) provides no electrical rerouting for the molded package; a thermal interface material (40) applied to the aluminum layer (21, 30) of each IMS (20); and a cooling system (70, 90) thermally connected to each IMS (20) through the thermal interface material (40) (See Lee Fig. 2, Fig. 3, Fig. 6, ¶ 0027-¶ 0035, ¶ 0050, ¶ 0051 and Palagashvili Fig. 1, ¶ 0032, ¶ 0036) (Notes: the circuit board to support and connect the power semiconductor devices is well-known and the copper layer is insulated by the organic isolation layer such that no rerouting to the aluminum layer is provided, which is the same as shown in FIG. 1 of the Application and as the recited elements. Further, having the power semiconductor dies to supply power and drive the LED chip is well-known in the art. Lastly, the exposed cooling system to dissipate heat directly and indirectly connects to the IMS via the thermal interface material). As to claim 11, Lee further discloses wherein the aluminum layer (21, 30) of each IMS (20) is thicker than the thermal interface material (40) (See Fig. 2). As to claim 18, Lee in view of Palagashvili further discloses wherein each of the molded packages is surface mounted to the circuit board (12 module, communication substrate) (See Lee Fig. 2, Fig. 3, ¶ 0032). As to claim 20, Lee in view of Palagashvili further discloses wherein for each power semiconductor device, the copper layer (23) of the IMS (20) is glued, soldered, or welded to the metallic region (15, 16) exposed at the side of the molded package that faces away from the circuit board (12 module, communication substrate) (See Lee Fig. 2) (Notes: the physical attachment is glued).
Claim(s) 2-3 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0025944 A1 to Lee et al. (“Lee”) in view of U.S. Patent Application Publication No. 2013/0208473 A1 to Palagashvili et al. (“Palagashvili”) as applied to claims 1 and 10 above, and further in view of CN-202293492-U to Qin et al. (“Qin”). The teachings of Lee and Palagashvili have been discussed above. As to claim 2, Lee in view of Qin further discloses wherein the aluminum layer (21, 30) of the IMS (20) has a thickness in a range of 0.5 mm to 5 mm, and wherein the organic isolation layer (22) of the IMS (20) has a thickness in a range of 5 μm to 250 μm (See Qin ¶ 0007-¶ 0010) such that heat conducting performance is greatly improved. As to claim 3, Lee in view of Qin further discloses wherein the copper layer (23) of the IMS (20) has a thickness in a range of 35 μm to 350 μm (See Qin ¶ 0007-¶ 0010). As to claim 16, Lee in view of Qin further discloses wherein the aluminum layer (21, 30) of each IMS (20) has a thickness in a range of 0.5 mm to 5 mm, and wherein the organic isolation layer (22) of each IMS (20) has a thickness in a range of 5 μm to 250 μm (See Qin ¶ 0007-¶ 0010) such that heat conducting performance is greatly improved. As to claim 17, Lee in view of Qin further discloses wherein the copper layer (23) of each IMS (20) has a thickness in a range of 35 μm to 350 μm (See Qin ¶ 0007-¶ 0010).
Claim(s) 8 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0025944 A1 to Lee et al. (“Lee”) in view of U.S. Patent Application Publication No. 2013/0208473 A1 to Palagashvili et al. (“Palagashvili”) as applied to claims 6 and 10 above, and further in view of CN-202293492-U to Qin et al. (“Qin”) and CN-211896756-U to Jiang et al. (“Jiang”). The teachings of Lee and Palagashvili have been discussed above.
As to claims 8 and 12, Lee in view of Qin and Jiang further discloses wherein the aluminum layer (21, 30) of the (each) IMS (20) has a thickness in a range of 0.5 mm to 5 mm, and wherein the thermal interface material (4) has a thickness in a range of 100 μm to 500 μm (See Qin ¶ 0007-¶ 0010 and Jiang Fig. 1, Embodiment 1, Embodiment 3, Page 1-Page 5) such that heat conducting performance is greatly improved and thermal interface material about partially separated from and below the organic isolation layer provides heat conducting fillers to improve the heat dissipation while the organic isolation layer provides the better bonding effect. As to claim 13, Lee in view of Qin and Jiang discloses further comprising metallic debris (heat conducting filler) trapped between the cooling system (70, 90) and one or more of the power semiconductor devices (11, 17/17), wherein a combined thickness of the thermal interface material (4) and the aluminum layer (21, 30) of each IMS (20) is greater than a thickness of the metallic debris (heat conducting filler) such that the metallic debris (heat conducting filler) is confined outside the organic isolation layer (22/3) of each IMS (20) (See Qin ¶ 0018-¶ 0019 and Jiang Fig. 1, Embodiment 1, Embodiment 3, Page 1-Page 5) such that thermal interface material about partially separated from and below the organic isolation layer provides heat conducting fillers or metal debris to improve the heat dissipation while the organic isolation layer provides the better bonding effect. As to claim 14, Lee in view of Qin and Jiang discloses further comprising metallic debris (heat conducting filler) trapped between the cooling system (70, 90) and one or more of the power semiconductor devices (11, 17/17) and having a thickness up to 600 μm, wherein a combined thickness of the thermal interface material (4) and the aluminum layer (21, 30) of each IMS (20) is greater than 600 μm (See Qin ¶ 0007-¶ 0010, ¶ 0018-¶ 0019 and Jiang Fig. 1, Embodiment 1, Embodiment 3, Page 1-Page 5) such that heat conducting performance is greatly improved and thermal interface material about partially separated from and below the organic isolation layer provides heat conducting fillers or metal debris to improve the heat dissipation while the organic isolation layer provides the better bonding effect. As to claim 15, Lee in view of Qin and Jiang discloses further comprising metallic debris (heat conducting filler) trapped between the cooling system (70, 90) and one or more of the power semiconductor devices (11, 17/17), wherein the metallic debris (heat conducting filler) penetrates the thermal interface material (4) and the aluminum layer (21, 30) of at least one IMS (20) but not the organic isolation layer (22/3) of any IMS (20) (See Qin ¶ 0007-¶ 0010, ¶ 0018-¶ 0019 and Jiang Fig. 1, Embodiment 1, Embodiment 3, Page 1-Page 5) such that heat conducting performance is greatly improved and thermal interface material about partially separated from and below the organic isolation layer provides heat conducting fillers or metal debris to improve the heat dissipation while the organic isolation layer provides the better bonding effect.
Further, the applicant also has not established the critical nature of the “thicknesses.” “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims….In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have various ranges. It would also have been obvious to one of ordinary skill in the art at the time the invention was made to discover the optimum or workable ranges by routine experimentations to obtain optimized “thicknesses” in light of design requirements and constrains such as conductive and insulating properties and overall dimensions. See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Claim(s) 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0025944 A1 to Lee et al. (“Lee”) and U.S. Patent Application Publication No. 2013/0208473 A1 to Palagashvili et al. (“Palagashvili”) as applied to claim 1 above, and further in view of CN-208336270-U to Huang et al. (“Huang”). The teachings of Lee and Palagashvili have been discussed above. As to claim 21, although Lee and Palagashvili do not further disclose wherein each one of the one or more power semiconductor dies is a power transistor die or a half bridge die, Huang does disclose wherein each one of the one or more power semiconductor dies (1) is a power transistor die (1) or a half bridge die (See Fig. 2, Page 1-Page 4). In view of the teaching of Huang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee and Palagashvili to have wherein each one of the one or more power semiconductor dies is a power transistor die or a half bridge die because the power transistor die provides reduced volume, simplifies the packaging process, high power factor, and higher driving power (See Page 2, Page 3). As to claim 22, although Lee and Palagashvili do not further disclose wherein each one of the one or more power semiconductor dies is a power Si MOSFET die, an IGBT die, a SiC MOSFET die, or a GaN HEMT die, Huang does disclose wherein each one of the one or more power semiconductor dies (1) is a power Si MOSFET die, an IGBT die, a SiC MOSFET die, or a GaN HEMT die (1) (See Fig. 2, Page 1-Page 4). In view of the teaching of Huang, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee and Palagashvili to have wherein each one of the one or more power semiconductor dies is a power Si MOSFET die, an IGBT die, a SiC MOSFET die, or a GaN HEMT die because the GaN HEMT die provides reduced volume, simplifies the packaging process, high power factor, and higher driving power (See Page 2, Page 3).
Claim(s) 23 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0025944 A1 to Lee et al. (“Lee”) and U.S. Patent Application Publication No. 2013/0208473 A1 to Palagashvili et al. (“Palagashvili”) as applied to claim 1 above, and further in view of CN-104654056-A to Li (“Li”). The teachings of Lee and Palagashvili have been discussed above. As to claim 23, although Lee and Palagashvili do not further disclose wherein the power electronics circuit is a DC/AC inverter, a DC/DC converter, an AC/DC converter, a DC/AC converter, an AC/AC converter, a multi-phase inverter, or an H-bridge, Li does disclose wherein the power electronics circuit (5) is a DC/AC inverter, a DC/DC converter, an AC/DC converter, a DC/AC converter, an AC/AC converter, a multi-phase inverter, or an H-bridge (See Fig. 1, Page 1-Page 3). In view of the teaching of Li, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lee and Palagashvili to have wherein the power electronics circuit is a DC/AC inverter, a DC/DC converter, an AC/DC converter, a DC/AC converter, an AC/AC converter, a multi-phase inverter, or an H-bridge, Li does disclose wherein the power electronics circuit (5) is a DC/AC inverter, a DC/DC converter, an AC/DC converter, a DC/AC converter, an AC/AC converter, a multi-phase inverter, or an H-bridge because high integration and stable and reliable power supply are obtained (See Page 3).
Response to Arguments
Applicant's arguments filed on March 24, 2026 have been fully considered but they are not persuasive. Applicant argues “but does not reroute or redistribute the primary current pathway of the power semiconductor device…then cathode lead frame 15 and anode lead frame 16 would be electrically sorted to together...Copper layer 23 of light source PCB 20 must provide some electrical rerouting to ensure that Lee’s LED package 10 is properly driven via the ‘circuit patterns’ formed on light source PCB 20.” This is not found persuasive because the limitation suggests the “no electrical rerouting for the molded package” is provided via the electrical isolation from the organic isolation layer. Specifically, the organic isolation layer provides the electrical isolation between the copper layer and the aluminum layer such that no “electrical rerouting” is formed from the aluminum layer to the copper layer. This is consistent with the disclosure in [0023] of the Specification, where “[a]n organic isolation layer 126 such as epoxy, polyimide, etc. electrically isolates the copper layer 122 and the aluminum layer 124 from one another, such that the copper layer 122 provides no electrical rerouting or redistribution for the molded package 102.” Thus, the negative limitation is directed to the electrical isolation provided by the organic isolation layer and not whether the copper layer is electrically conductive or not.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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