DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Device Embodiment 2 in the reply filed on 11/26/2025 is acknowledged. The traversal is on the ground(s) that features in the species noted by Examiner are not mutually exclusive and searching for two species would not be an search burden. This is not found persuasive because as noted in the restriction: The species are independent or distinct because as can be seen from the figures, viewing Fig 2A, it is seen that in the device of Embodiment 1, the top of STI1 and STI3 are all at the same level LV1. In Fig 5, it is seen that in the device of Embodiment 2 the top of STI3 is higher than the level of STI1. In addition, as shown in Fig 2B of Device Embodiment 1, protrusions of STI3 have straight sides while in Fig 6 of Device Embodiment 2, the protrusions of STI3 show sides where the width of the taper changes at a level LV2, which create CAc and CAb, level LV2 is higher than LV1. Then a second tapered part of STI3 continues from LV2 to a point below LV1. In addition, these species are not obvious variants of each other based on the current record.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 6-8, 11-12, 16-17 and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo et al. (US 2021/0351189 A1, hereinafter Luo ‘189).
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With respect to Claim 1 Luo ‘189 discloses a semiconductor device (FIG 1-12) comprising:
an active pattern (202, Fig 2, Para [0020]) extending along a first direction (X direction as shown in Fig 5); and
a first word line (left 205 as shown in annotated Fig 9 of Luo ‘189, Para [0039], hereinafter FWL) and a second word line (right 205 as shown in annotated Fig 9 of Luo ‘189, Para [0039], hereinafter SWL) which intersect (disclosed in annotated Fig 9 of Luo ‘189) the active pattern (202), wherein the active pattern (202) comprises a center active portion (center portion of 202 as shown in annotated Fig 9 of Luo ‘189, hereinafter CAP) between the first word line (FWL) and the second word line (SWL)(disclosed in annotated Fig 9 of Luo ‘189),
wherein the center active portion (CAP) comprises,
a center portion (center portion of CAP as shown in annotated Fig 9_2 of Luo '189, hereinafter CP) extending from the first word line (FWL) to the second word line (SWL)(extension shown in annotated Fig 9_2 of Luo ‘189),
a first center protrusion (first center protrusion as shown in annotated Fig 9_2 of Luo ‘189, hereinafter FCP) protruding from one side surface (upper side of CP as shown in annotated Fig 9_2 of Luo ‘189) of the center portion (CP) in a second direction (-y2 direction as shown in annotated Fig 9_2 of Luo ‘189, -y2 defined in Fig 5) intersecting the first direction (X direction), and
a second center protrusion (second center protrusion as shown in annotated Fig 9_2 of Luo ‘189, hereinafter SCP) protruding from another side surface (lower side of CP as shown in annotated Fig 9_2 of Luo ‘189) of the center portion (CP) in an opposite direction (y2 direction as shown in annotated Fig 9_2 of Luo ‘189, y2 defined in Fig 5) to the second direction (-y2 direction),
wherein the first center protrusion (FCP) extends from the first word line (FWL) along the first direction (X direction as shown in annotated Fig 9_2 of Luo ‘189), and
wherein the second center protrusion (SCP) extends from the second word line (SWL) along an opposite direction (-X direction as shown in annotated Fig 9_2 of Luo ‘189) to the first direction (X direction).
With respect to Claim 4 Luo ‘189 discloses all limitations of the semiconductor device of claim 1, and Luo ‘189 discloses further wherein the center portion (CP), the first center protrusion (FCP), and the second center protrusion (SCP) are connected to each other without interfaces therebetween (Fig 9 and Fig 10 disclose CP, FCP and SCP connected without interfaces, as shown in Fig 10, 202 is connected under areas 205a).
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With respect to Claim 6 Luo ‘189 discloses all limitations of the semiconductor device of claim 1, and Luo ‘189 discloses further comprising:
a device isolation pattern (203, Fig 10, Para [0050]) surrounding the active pattern (202, Fig 10, Para [0050] disclose 202 isolated by 203),
wherein the device isolation pattern (203) protrudes from a side surface (side of 202 as shown in annotated Fig 10 of Luo ‘189) of the active pattern (202) toward an inside of the active pattern (202)(annotated Fig 10 of Luo ‘189 discloses 203 protrudes from side of 202 toward inside of 202).
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With respect to Claim 7 Luo ‘189 discloses all limitations of the semiconductor device of claim 1, and Luo ‘189 discloses further wherein the active pattern (202) further comprises:
a first edge active portion (first edge active portion, as shown in annotated Fig 9 of Luo ‘189, hereinafter FAE) and a second edge active portion (second edge active portion, as shown in annotated Fig 9 of Luo ‘189, hereinafter SAE), which are spaced apart from each other (FAE and SAE spaced apart is disclosed in annotated Fig 9 of Luo ‘189) with the center active portion (CAP) interposed therebetween (shown in annotated Fig 9 of Luo ‘189), wherein
the first word line (FWL) is between the center active portion (CAP) and the first edge active portion (FAE)(FWL between CAP and FAE shown in annotated Fig 9 of Luo ‘189),
the second word line (SWL) is between the center active portion (CAP) and the second edge active portion (SAE) (SWL between CAP and SAE shown in annotated Fig 9 of Luo ‘189),
the first edge active portion (FAE) comprises a first edge portion (first edge portion shown in annotated Fig 9_3 of Luo ‘189, hereinafter FEP), a first round portion (first round portion shown in annotated Fig 9_3 of Luo ‘189, hereinafter FRP) surrounding an end portion (end portion shown in annotated Fig 9_3 of Luo ‘189) of the first edge portion (FEP), and a first edge protrusion (first edge protrusion shown in annotated Fig 10 of Luo ‘189, hereinafter 1EP) protruding from one side surface (side of FEP shown in annotated Fig 9_3 of Luo ‘189) of the first edge portion (FEP),
the second edge active portion (SAE) comprises a second edge portion (second edge portion shown in annotated Fig 9_3 of Luo ‘189, hereinafter SEP), a second round portion (first round portion shown in annotated Fig 9_3 of Luo ‘189, hereinafter SRP) surrounding an end portion (end portion shown in annotated Fig 9_3 of Luo ‘189) of the second edge portion (SEP), and
a second edge protrusion (second edge protrusion shown in annotated Fig 10 of Luo ‘189, hereinafter 2EP) protruding from one side surface (side of SEP shown in annotated Fig 9_3 of Luo ‘189) of the second edge portion (SEP).
With respect to Claim 8 Luo ‘189 discloses all limitations of the semiconductor device of claim 7, and Luo ‘189 further discloses wherein the first edge protrusion (1EP) extends from the first word line (FWL) along the opposite direction (-X direction) to the first direction (X direction)(shown in annotated Fig 9_3 of Luo ‘189), and
the second edge protrusion (2EP) extends from the second word line (SWL) along the first direction (X direction) (shown in annotated Fig 9_3 of Luo ‘189).
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With respect to Claim 11 Luo ‘189 discloses all limitations of the semiconductor device of claim 7, and Luo ‘189 discloses further wherein the active pattern (202) further comprises:
a first middle active portion (area under first 205a as shown in annotated Fig 10_2 of Luo ‘189, hereinafter FMAP) under the first word line (FWL, (left 205) as shown in annotated Fig 10_2 of Luo ‘189) and between the center active portion (CAP as shown in annotated Fig 10_2 of Luo ‘189) and the first edge active portion (FEP as shown in annotated Fig 10_2 of Luo ‘189); and
a second middle active portion (area under second 205a as shown in annotated Fig 10_2 of Luo ‘189, hereinafter SMAP) under the second word line (SWL, (right 205) as shown in annotated Fig 10_2 of Luo ‘189) and between the center active portion (CAP as shown in annotated Fig 10_2 of Luo ‘189) and the second edge active portion (SEP as shown in annotated Fig 10_2 of Luo ‘189).
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With respect to Claim 12 Luo ‘189 discloses all limitations of the semiconductor device of claim 11, and Luo ‘189 further discloses wherein
the first middle active portion (FMAP) comprises a first middle portion (first middle portion as shown in annotated Fig 9_4 of Luo ‘189, hereinafter FMP), and a first middle protrusion (first middle protrusion as shown in annotated Fig 9_4 of Luo ‘189, hereinafter 1MP) protruding from one side surface (side of FMP) of the first middle portion (FMP),
the second middle active portion (FMAP) comprises a second middle portion (second middle portion as shown in annotated Fig 9_4 of Luo ‘189, hereinafter SMP) and a second middle protrusion (second middle protrusion as shown in annotated Fig 9_4 of Luo ‘189, hereinafter 2MP) protruding from one side surface (side of SMP) of the second middle portion (SMP),
the first middle protrusion (1MP) connects the first center protrusion (FCP) and the first edge protrusion (1FEP)(arrangement shown in annotated Fig 9_4 of Luo ‘189), and
the second middle protrusion (2MP) connects the second center protrusion (SCP) and the second edge protrusion (2SEP) (arrangement shown in annotated Fig 9_4 of Luo ‘189).
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With respect to Claim 16 Luo ‘189 discloses a semiconductor device (FIG 1-12) comprising:
active patterns (202, Fig 2, Para [0020]), each of which extends along a first direction (X direction as shown in Fig 5); and
a device isolation pattern (203, Fig 10, Para [0050]) surrounding each of the active patterns (202, Fig 10, Para [0050] disclose 202 isolated by 203),
wherein the active patterns (202) comprise,
a first active pattern (first 202 as shown in annotated Fig 9_5 of Luo ‘189, hereinafter 1stAP),
a second active pattern (second 202 as shown in annotated Fig 9_5 of Luo ‘189, hereinafter 2ndAP) spaced apart (disclosed in annotated Fig 9_5 of Luo ‘189) from the first active pattern (1stAP) in the first direction (X direction),
a third active pattern (third 202 as shown in annotated Fig 9_5 of Luo ‘189, hereinafter 3rdAP) spaced apart (disclosed in annotated Fig 9_5 of Luo ‘189) from the first active pattern (1stAP) and the second active patterns (2ndAP) in a second direction (y1 as show in Fig 5 and annotated Fig 9_5 of Luo ‘189) that intersects the first direction (X direction); and
a fourth active pattern (fourth 202 as shown in annotated Fig 9_5 of Luo ‘189, hereinafter 4thAP) spaced apart (disclosed in annotated Fig 9_5 of Luo ‘189) from the first active pattern (1stAP) and the second active patterns (2ndAP) in direction opposite (-y1 direction) to the second direction (y1),
wherein the device isolation pattern (203) comprises,
first device isolation patterns (first device isolation patterns shown in annotated Fig 9_5 of Luo ‘189, hereinafter 1DIP) between the first active pattern (1stAP) and the third active pattern (3rdAP) and between the second active pattern (2ndAP) and the fourth active pattern (4thAP), and
second device isolation patterns (second device isolation patterns shown in annotated Fig 9_5 of Luo ‘189, hereinafter 2DIP) between the first active pattern (1stAP) and the fourth active pattern (4thAP) and between the second active pattern (2ndAP) and the third active pattern (3rdAP),
wherein each of the first device isolation patterns (1DIP) and the second device isolation patterns (2DIP) protrudes from a side surface of an adjacent active pattern toward an inside (center portion) of the adjacent active pattern (annotated Fig 9_5 of Luo ‘189 discloses 1DIP extending from sides of 1stAP and 2ndAP toward an inside (center portion) of 3rdAP and 4thAP respectively) (annotated Fig 9_5 of Luo ‘189 discloses 2DIP extending from sides of 1stAP and 2ndAP toward an inside (center portion) of 4thAP and 3rdAP respectively).
With respect to Claim 17 Luo ‘189 disclose all limitations of the semiconductor device of claim 16, and Luo ‘189 discloses further wherein a length (length of 1DIP) of each of the first device isolation patterns (1DIP) in the first direction (X direction) is greater than a length of each (length of 2DIP) of the second device isolation patterns (2DIP) in the first direction (X direction)(annotated Fig 9_5 of Luo ‘189 discloses 1DIP extends from end of active region through word line 205 through center active portion while 2DIP extends from end of active region through word line 205, therefore 1DIP has a greater length in the X direction than 2DIP).
With respect to Claim 19 Luo ‘189 discloses all limitations of the semiconductor device of claim 16, and Luo ‘189 further discloses wherein each of the first device isolation patterns (1DIP) and the second device isolation patterns (2DIP) includes at least one of silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (A12O3), lanthanum oxide (La2O3), aluminum nitride (AIN), or silicon oxynitride (SiON)(Para [0022] discloses isolation areas 203 as silicon oxide).
With respect to Claim 20 Luo ‘189 discloses all limitations of the semiconductor device of claim 16, and Luo ‘189 discloses further comprising:
word lines (205, Fig 9, Para [0039]) intersecting the active patterns (1stAP) and the first device isolation patterns (1DIP)(205 intersecting 1stAP and 1DIP disclosed in annotated Fig 9_5 of Luo ‘189).
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With respect to Claim 21 Luo ‘189 discloses all limitations of the semiconductor device of claim 16, and Luo ‘189 further discloses wherein the device isolation pattern (203) further comprises a third device isolation pattern (third device isolation pattern shown in annotated Fig 9_5 of Luo ‘189, hereinafter 3DIP) surrounded by the first active pattern (1stAP), the second active pattern (2ndAP), the third active pattern (3rdAP), and the fourth active patterns (4thAP)(3DIP surrounded by the four active patterns is shown in annotated Fig 9_5 of Luo ‘189), and the third device isolation pattern (3DIP) does not protrude toward insides (center portions) of the active patterns (1stAP/2ndAP/3rdAP/4thAP)(annotated Fig 9_5 discloses 3DIP does not protrude toward center portions of active patterns).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Luo ‘189 in view of Liu (US 2022/0310615 A1, hereinafter Liu ‘615), in view of the following arguments.
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With respect to Claim 2 Luo ‘189 discloses all limitations of the semiconductor device of claim 1, but Luo ‘189 fails to explicitly disclose wherein the first center protrusion is spaced apart from the second word line, and the second center protrusion is spaced apart from the first word line.
Nevertheless, in a related endeavor (Fig 4-6 of Liu ‘615), Liu ‘615 teaches wherein the first center protrusion (side of 130, shown in annotated Fig 4 of Liu ‘615, Para [0045]) is spaced apart (shown in annotated Fig 4 of Liu ‘615) from the second word line (lower 200, Fig 4 of Liu ‘615, Para [0045]), and the second center protrusion (side of 130, shown in annotated Fig 4 of Liu ‘615, Para [0045]) is spaced apart (shown in annotated Fig 4 of Liu ‘615) from the first word line (upper 200, Fig 4 of Liu ‘615, Para [0045]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Liu ‘615’s teaching of wherein the first center protrusion is spaced apart from the second word line, and the second center protrusion is spaced apart from the first word line into Luo ‘189’s device. Luo ‘189 teaches a memory device with shaped active areas. Liu ‘615 also teaches (Para [0046]) a memory device with shaped active areas and further teaches the shape wherein the first center protrusion is spaced apart from the second word line, and the second center protrusion is spaced apart from the first word line reduces the possibility of parasitic capacitance. Therefore, the ordinary artisan would have been motivated to modify Luo ‘189 in the manner set forth above, at least, to reduce the possibility of parasitic capacitance in the device.
As incorporated, the active region shape of Liu ‘615 as described above would be used in active pattern (202) of Luo ‘189.
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With respect to Claim 3 Luo ‘189 discloses all limitations of the semiconductor device of claim 1, but Luo ‘189 fails to explicitly disclose wherein a length of the center portion in the first direction is greater than a length of the first center protrusion in the first direction, and is greater than a length of the second center protrusion in the first direction.
Nevertheless, in a related endeavor (Fig 4-6 of Liu ‘615), Liu ‘615 teaches wherein a length of the center portion (length of CP as shown in annotated Fig 4_2 of Liu ‘615) in the first direction (second direction of annotated Fig 4_2 of Liu ‘615 is same direction as first direction of instant application) is greater than a length of the first center protrusion (FCP) in the first direction (second direction), and is greater than a length of the second center protrusion (SCP) in the first direction (second direction)(annotated Fig 4_2 of Liu ‘615 discloses the length of CP is greater than the length of FCP and SCP in the second direction (equivalent to first direction of instant application).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Liu ‘615’s teaching of wherein the first center protrusion is spaced apart from the second word line, and the second center protrusion is spaced apart from the first word line into Luo ‘189’s device. Luo ‘189 teaches a memory device with shaped active areas. Liu ‘615 also teaches (Para [0046]) a memory device with shaped active areas and further teaches the shape wherein the first center protrusion is spaced apart from the second word line, and the second center protrusion is spaced apart from the first word line reduces the possibility of parasitic capacitance. Therefore, the ordinary artisan would have been motivated to modify Luo ‘189 in the manner set forth above, at least, to reduce the possibility of parasitic capacitance in the device.
As incorporated, the active region shape of Liu ‘615 as described above would be used in active pattern (202) of Luo ‘189.
Claims 13-15 and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Luo ‘189 in view of Ryu et al. (US 2022/0045063 A1, hereinafter Ryu ‘063), in view of the following arguments.
With respect to Claim 13 Luo ‘189 discloses all limitations of the semiconductor device of claim 1, but Luo ‘189 fails to explicitly disclose wherein a profile of each of a first and a second side surfaces of the active pattern has an uneven shape.
Nevertheless, in a related endeavor (Fig 28A-28B of Ryu ‘063), Ryu ‘063 teaches wherein a profile (side view of Fig 28B of Ryu ‘063) of each of a first (left sides of 312b, Fig 28B of Ryu ‘063, Para [0071]) and a second side surfaces (right sides of 312b, Fig 28B of Ryu ‘063, Para [0071]) of the active pattern (ACT, Fig 28B of Ryu ‘063, Para [0071]) has an uneven shape (Fig 28B of Ryu ‘063 discloses sides of 312b have an uneven shape).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ryu ‘063’s teaching of a profile of each of a first and a second side surfaces of the active pattern has an uneven shape into Luo ‘189’s device. Luo ‘189 and Ryu ‘063 both teach memory structures where active areas and insulating regions having specific shapes. The ordinary artisan would therefore have been motivated to modify Luo ‘189 in the manner set forth above, at least, because, as taught in Para (0068), this uneven shape of the side surfaces of the active shape provides an additional layer of insulation between the active regions and the conductive structures of the data storage regions. Therefore the shape would provide additional protection against parasitic capacitance within the device.
As incorporated, the uneven shapes of the sides of the active patterns taught by Ryu ‘063 would be used in the active patterns (202) of Luo ‘189.
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With respect to Claim 14 Luo ‘189 discloses all limitations of the semiconductor device of claim 1, but Luo ‘189 fails to explicitly disclose wherein a bottommost surface of the first word line and a bottommost surface of the second word line are at a first level, a bottommost surface of the first center protrusion and a bottommost surface of the second center protrusion are at a second level, and the second level is above the first level.
Nevertheless, in a related endeavor (Fig 28A-28B of Ryu ‘063), Ryu ‘063 teaches wherein a bottommost surface (bottom of left WL as shown in annotated Fig 28B of Ryu ‘063) of the first word line (left WL, Fig 28B of Ryu ‘063, Para [0072]) and a bottommost surface (bottom of right WL as shown in annotated Fig 28B of Ryu ‘063) of the second word line (right WL, Fig 28B of Ryu ‘063, Para [0072]) are at a first level (first level shown in annotated Fig 28B of Ryu ‘063), a bottommost surface (bottommost surface of straight side of 312a as shown in annotated Fig 28B of Ryu ‘063) of the first center protrusion (312a, Fig 28B of Ryu ‘063, Para [0071]) and a bottommost surface (bottommost surface of straight side of 312a as shown in annotated Fig 28B of Ryu ‘063) of the second center protrusion (312a, Fig 28B of Ryu ‘063, Para [0071])(Fig 28B of Ryu ‘063 shows one representative area 312a; Fig 28A of Ryu ‘063 and Para [0070] disclose a plurality of 312a in active regions ACT) are at a second level (second level as shown in annotated Fig 28B of Ryu ‘063), and the second level (second level as shown in annotated Fig 28B of Ryu ‘063) is above the first level (first level shown in annotated Fig 28B of Ryu ‘063)(second level above first level shown in annotated Fig 28B of Ryu ‘063).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ryu ‘063’s teaching of wherein a bottommost surface of the first word line and a bottommost surface of the second word line are at a first level, a bottommost surface of the first center protrusion and a bottommost surface of the second center protrusion are at a second level, and the second level is above the first level into Luo ‘189’s device. Luo ‘189 and Ryu ‘063 both teach memory structures where active areas and insulating regions having specific shapes but Luo ‘189 provides limited details around the formation of the word line structure. The ordinary artisan would therefore have been motivated to modify Luo ‘189 in the manner set forth above, at least, because, as Ryu ‘063 provides a more detailed description of the word line structure within the active region. Therefore combining Luo ‘189 with Ryu ‘063 would provide the person with ordinary skill in the art improved manufacturing details for the memory device.
As incorporated, the teaching of Ryu ‘063, wherein a bottommost surface of the first word line and a bottommost surface of the second word line are at a first level, a bottommost surface of the first center protrusion and a bottommost surface of the second center protrusion are at a second level, and the second level is above the first level would be used as the word line (205) and active region (202) layout of Luo ‘189’s device.
With respect to Claim 15 Luo ‘189 discloses all limitations of the semiconductor device of claim 1, but Luo ‘189 fails to explicitly disclose wherein a bottommost surface of the first word line and a bottommost surface of the second word line are at a first level, and one side surface of the active pattern under the first level has a straight profile.
Nevertheless, in a related endeavor (Fig 28A-28B of Ryu ‘063), Ryu ‘063 teaches wherein a bottommost surface (bottom of left WL as shown in annotated Fig 28B of Ryu ‘063) of the first word line (left WL, Fig 28B of Ryu ‘063, Para [0072]) and a bottommost surface (bottom of right WL as shown in annotated Fig 28B of Ryu ‘063) of the second word line (right WL, Fig 28B of Ryu ‘063, Para [0072]) are at a first level (first level shown in annotated Fig 28B of Ryu ‘063), and one side surface (left side of ACT as shown in annotated Fig 28B of Ryu ‘063) of the active pattern (ACT, Fig 28B of Ryu ‘063, Para [0071]) under the first level (first level shown in annotated Fig 28B of Ryu ‘063) has a straight profile (disclosed in annotated Fig 28B of Ryu ‘063).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ryu ‘063’s teaching of wherein a bottommost surface of the first word line and a bottommost surface of the second word line are at a first level, and one side surface of the active pattern under the first level has a straight profile into Luo ‘189’s device. Luo ‘189 and Ryu ‘063 both teach memory structures where active areas and insulating regions having specific shapes but Luo ‘189 provides limited details around the formation of the word line structure. The ordinary artisan would therefore have been motivated to modify Luo ‘189 in the manner set forth above, at least, because, as Ryu ‘063 provides a more detailed description of the word line structure within the active region. Therefore combining Luo ‘189 with Ryu ‘063 would provide the person with ordinary skill in the art improved manufacturing details for the memory device.
As incorporated, the teaching of Ryu ‘063, wherein a bottommost surface of the first word line and a bottommost surface of the second word line are at a first level, and one side surface of the active pattern under the first level has a straight profile would be used as the word line (205) and active region (202) layout and profiles of Luo ‘189’s device.
With respect to Claim 22 Luo ‘189 discloses all limitations of the semiconductor device of claim 16, but Luo ‘189 fails to explicitly disclose wherein each of the active patterns comprises an upper active pattern and a lower active pattern, and each of the first device isolation patterns and the second device isolation patterns does not protrude toward an inside of the lower active pattern of the adjacent active pattern.
Nevertheless, in a related endeavor (Fig 28A-28B of Ryu ‘063), Ryu ‘063 teaches wherein each of the active patterns (ACT, Fig 28B of Ryu ‘063, Para [0071]) comprises an upper active pattern (upper active pattern disclosed in annotated Fig 28B_2 of Ryu ‘063) and a lower active pattern (lower active pattern disclosed in annotated Fig 28B_2 of Ryu ‘063), and each of the first device isolation patterns (first device isolation patterns shown in annotated Fig 28B of Ryu ‘063, Para [0069]) and the second device isolation patterns (first device isolation patterns shown in annotated Fig 28B of Ryu ‘063, Para [0069]) does not protrude toward an inside of the lower active pattern (lower active pattern disclosed in annotated Fig 28B_2 of Ryu ‘063) of the adjacent active pattern (ACT)(annotated Fig 28B_2 of Ryu ‘063 discloses that the isolation regions are straight in the lower active pattern regions so they do not protrude toward an inside of adjacent lower active pattern).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ryu ‘063’s teaching of wherein each of the active patterns comprises an upper active pattern and a lower active pattern, and each of the first device isolation patterns and the second device isolation patterns does not protrude toward an inside of the lower active pattern of the adjacent active pattern into Luo ‘189’s device. Luo ‘189 and Ryu ‘063 both teach memory structures where active areas and insulating regions having specific shapes but Luo ‘189 does not provide the details, in a profile, of the active region and insulating regions that are provided in Ryu ‘063. The ordinary artisan would therefore have been motivated to modify Luo ‘189 in the manner set forth above, at least, because, as taught in Para (0068) of Ryu ‘168, the uneven shape of the upper side surfaces of the active shape provides an additional layer of insulation between the active regions and the conductive structures of the data storage regions, this level of isolation would not then be needed at the lower levels of the active structure. Therefore the shape would provide additional protection against parasitic capacitance at the top of the structure and a simplified manufacturing structure, with the straight sides of the lower active region.
As incorporated, Ryu ‘063’s teaching of wherein each of the active patterns comprises an upper active pattern and a lower active pattern, and each of the first device isolation patterns and the second device isolation patterns does not protrude toward an inside of the lower active pattern of the adjacent active pattern would be used in the shapes of active patterns (202) and isolation regions (203) of Luo ‘189
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With respect to Claim 23 Luo ‘189 discloses a semiconductor device (Fig 1-12) comprising:
a substrate (201, Fig 2, Para [0020]);
an active pattern (202, Fig 2, Para [0020]) on the substrate (201) and extending along a first direction parallel (x direction as shown in Fig 5) to a bottom surface (bottom of 201) of the substrate (201), the active pattern (202) comprising a first edge active portion (first edge active portion, as shown in annotated Fig 9 of Luo ‘189, hereinafter FAE), a second edge active portion (second edge active portion, as shown in annotated Fig 9 of Luo ‘189, hereinafter SAE), and a center active portion (center portion of 202 as shown in annotated Fig 9 of Luo ‘189, hereinafter CAP) between the first edge active portion (FAE) and the second edge active portions (SEA)(arrangement disclosed in annotated Fig 9 of Luo ‘189);
a device isolation pattern (203, Fig 10, Para [0050]) surrounding the active pattern (202)(disclosed in Fig 9);
a first word line (left 205 as shown in annotated Fig 9 of Luo ‘189, Para [0039], hereinafter FWL) intersecting the active pattern (202) between the first edge active portion (FAE) and the center active portion (CAP) (FWL between CAP and FAE shown in annotated Fig 9 of Luo ‘189);
a second word line (right 205 as shown in annotated Fig 9 of Luo ‘189, Para [0039], hereinafter SWL) intersecting the active pattern (202) between the second edge active portion (SAE) and the center active portion (SAP) (SWL between CAP and SAE shown in annotated Fig 9 of Luo ‘189);
a bit line (Para [0048] discloses a bit line (not shown) formed over protective layer (212 of Fig 12)) extending on the active pattern (a bit line over protective layer (212 of Fig 12) extends on active pattern 202) and electrically connected to the center active portion(CAP)(Para [0048] discloses bit line (not shown) connected with the drain region and Para [0037] discloses the middle section of 202 to be the drain region);
wherein the center active portion (CAP) comprises,
a center portion (center portion of CAP as shown in annotated Fig 9_2 of Luo '189, hereinafter CP),
a first center protrusion (first center protrusion as shown in annotated Fig 9_2 of Luo ‘189, hereinafter FCP) protruding from the center portion (CP) in a second direction (-y2 direction as shown in annotated Fig 9_2 of Luo ‘189, -y2 defined in Fig 5) which is parallel (x and y directions are parallel to bottom of substrate as shown by axis in Fig 5) to the bottom surface of the substrate (bottom of 201) and intersects the first direction (X direction as shown on Fig 5), and
a second center protrusion (second center protrusion as shown in annotated Fig 9_2 of Luo ‘189, hereinafter SCP) protruding from the center portion (CP) in an opposite direction (y2 as shown in annotated Fig 9_2 of Luo ‘189) to the second direction (-y2),
wherein the first center protrusion (FCP) extends from the first word line (FWL) along the first direction (X direction)(shown in annotated Fig 9_2 of Luo ‘189), and
the second center protrusion (SCP) extends from the second word line (SWL) along an opposite direction (-X direction as shown in annotated Fig 9_2 of Luo ‘189) to the first direction (X direction)
But Luo ‘189 fails to explicitly disclose storage node contacts electrically connected to the first edge active portion and the second edge active portion, respectively; and data storage patterns electrically connected to the storage node contacts, respectively.
Nevertheless, in a related endeavor (Fig 28A-28B of Ryu ‘063), Ryu ‘063 teaches storage node contacts (BC, Fig 28B of Ryu ‘063, Para [0075]) electrically connected (Fig 28B of Ryu ‘063 discloses BC connected to 312b and BC as tungsten and 312b as a doped region, therefore the regions have an electrical connection) to the first edge active portion (left 312b, as shown in Fig 28B of Ryu ‘063, Para [0075]) and the second edge active portion (right 312b, as shown in Fig 28B of Ryu ‘063, Para [0075])(right BC (not labeled but shown in Fig 28B of Ryu ‘063 contacts right 312b), respectively; and data storage patterns (CAP, Fig 28B of Ryu ‘063, Para [0079]) electrically connected (Fig 28B of Ryu ‘063 and Para [0076] disclose BC connected to CAP by LP (formed of tungsten) therefore the regions have an electrical connection) to the storage node contacts (BC), respectively.
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ryu ‘063’s teaching of storage node contacts electrically connected to the first edge active portion and the second edge active portion, respectively; and data storage patterns electrically connected to the storage node contacts, respectively into Luo ‘189’s device. Luo ‘189 and Ryu ‘063 both teach memory structures where active areas and insulating regions having specific shapes but Luo ‘189 provides limited details around the formation of the device structure to connect to data storage regions. The ordinary artisan would then have been motivated to modify Luo ‘189 in the manner set forth above, at least, because by using the details of the storage node contacts as they electrically connect to the active regions would provide the ordinary artisan a proven structure and details that add valuable functions to the memory device.
As incorporated, Ryu ‘063’s teaching of storage node contacts electrically connected to the first edge active portion and the second edge active portion, respectively; and data storage patterns electrically connected to the storage node contacts would be used in the device of Luo ‘189.
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With respect to Claim 24 Luo ‘189 as modified by Ryu ‘063 discloses all limitations of the semiconductor device of claim 23, but Luo ‘189 as modified by Ryu ‘063 fails to explicitly disclose wherein the first center protrusion is spaced apart from the second word line, and the second center protrusion is spaced apart from the first word line.
Nevertheless, in a related endeavor (Fig 4-6 of Liu ‘615), Liu ‘615 teaches wherein the first center protrusion (side of 130, shown in annotated Fig 4 of Liu ‘615, Para [0045]) is spaced apart (shown in annotated Fig 4 of Liu ‘615) from the second word line (lower 200, Fig 4 of Liu ‘615, Para [0045]), and the second center protrusion (side of 130, shown in annotated Fig 4 of Liu ‘615, Para [0045]) is spaced apart (shown in annotated Fig 4 of Liu ‘615) from the first word line (upper 200, Fig 4 of Liu ‘615, Para [0045]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Liu ‘615’s teaching of wherein the first center protrusion is spaced apart from the second word line, and the second center protrusion is spaced apart from the first word line into Luo ‘189 as modified by Ryu ‘063’s device. Luo ‘189 as modified by Ryu ‘063 teaches a memory device with shaped active areas. Liu ‘615 also teaches (Para [0046]) a memory device with shaped active areas and further teaches the shape wherein the first center protrusion is spaced apart from the second word line, and the second center protrusion is spaced apart from the first word line reduces the possibility of parasitic capacitance. Therefore, the ordinary artisan would have been motivated to modify Luo ‘189 as modified by Ryu ‘063 in the manner set forth above, at least, to reduce the possibility of parasitic capacitance in the device.
As incorporated, the active region shape of Liu ‘615 as described above would be used in active pattern (202) of Luo ‘189 as modified by Ryu ‘063.
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898