Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (U.S. 2015/0221774 A1, hereinafter refer to Yamazaki) in view of Lee et al. (U.S. 2022/0157997 A1, hereinafter refer to Lee) and Zhang et al. (U.S. 2021/0135144 A1, hereinafter refer to Zhang).
Regarding Claim 1: Yamazaki discloses thin film transistor (see Yamazaki, Figs.17A-17B as shown below and ¶ [0002]) comprising:
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an active layer (130) (see Yamazaki, Figs.17A-17B as shown above); and
a gate electrode (170) partially overlapping the active layer (130) (see Yamazaki, Figs.17A-17B as shown above);
wherein the active layer (130) includes:
a channel portion (a portion of active layer 130 which overlaps the gate electrode 170) (see Yamazaki, Figs.17A-17B as shown above);
a first connection portion (a portion of active layer 130 which does not overlaps the gate electrode 170) at a first side of the channel portion (a portion of active layer 130 which overlaps the gate electrode 170) (see Yamazaki, Figs.17A-17B as shown above); and
a second connection portion (a portion of active layer 130 which does not overlaps the gate electrode 170) at a second side of the channel portion (a portion of active layer 130 which overlaps the gate electrode 170), the second connection portion being spaced apart from the first connection portion (see Yamazaki, Figs.17A-17B as shown above);
wherein the channel portion (a portion of active layer 130 which overlaps the gate electrode 170) includes:
a first channel part (333) overlapping the gate electrode (170) (see Yamazaki, Figs.17A-17B as shown above); and
wherein the active layer (130) includes:
a first active layer (130a/130b) (see Yamazaki, Figs.17A-17B as shown above); and
a second active layer (130c) on the first active layer (130a/130b) (see Yamazaki, Figs.17A-17B as shown above);
wherein the first channel part (333) includes the first active layer (130a/130b) and the second active layer (130c) (see Yamazaki, Figs.17A-17B as shown above);
wherein the channel portion (a portion of active layer 130 which overlaps the gate electrode 170), the first connection portion and the second connection portion are integrally formed (see Yamazaki, Figs.17A-17B as shown above).
Yamazaki is silent upon explicitly disclosing wherein the channel portion includes:
a first channel part overlapping the gate electrode; and
a second channel part not overlapping the gate electrode;
wherein the second channel part includes the first active layer;
wherein the first channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion, and
wherein the second channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion.
For support see Lee, which teaches wherein the channel portion (130) (see Lee, Figs.3 and 4 as shown below and ¶ [0004]) includes:
a first channel part overlapping the gate electrode (110) (see Lee, Fig.3 as shown below and ¶ [0004]); and
a second channel part not overlapping the gate electrode (110) (see Lee, Fig.3 as shown below and ¶ [0004]);
wherein the second channel part includes the first active layer (131) (see Lee, Fig.3 as shown below and ¶ [0004]);
wherein the first channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion (see Lee, Fig.3 as shown below and ¶ [0004]), and
wherein the second channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion (see Lee, Fig.3 as shown below and ¶ [0004]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki and Lee to form the configurations of Yamazaki’s thin film transistor according to the teachings of Lee thin film transistor configuration in order to obtain a thin film transistor capable of improving stability and performance.
The combination of Yamazaki and Lee is silent upon explicitly disclosing wherein the second active layer includes a material having greater mobility than the first active layer.
For support see Zhang, which teaches wherein the second active layer (5) includes a material having greater mobility than the first active layer (4) (see Zhang, Fig.9, ¶ [0045], and ¶ [0068]- ¶ [0072]).
The combination of Yamazaki and Lee teaches the claimed invention except for the material of the second active layer. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki, Lee, and Zhang to enable the second active layer includes a material having greater mobility than the first active layer as taught by Zhang in order to obtain the display substrate with a narrow bezel, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Regarding Claim 2: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the second channel part is configured to be driven by a fringing electric field generated by the gate electrode (110) (see Lee, Fig.3 as shown above).
Note: the discovery of a previously unappreciated property of the combination of Yamazaki, Lee, and Zhang prior art composition, or of a scientific explanation for the combination of Yamazaki, Lee, and Zhang prior art’s functioning, does not render the old composition patentably new to the discoverer.
Regarding Claim 3: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the active layer (130) is an oxide semiconductor layer including an oxide semiconductor material (see Yamazaki, Figs.17A-17B as shown above), and
wherein each of the first connection portion (331/332) and the second connection portion (331/332) is formed by selective conductorization of the oxide semiconductor layer (see Yamazaki, Figs.17A-17B as shown above).
Note: patentability of a product does not depend on its method of production.
Regarding Claim 4: Yamazaki as modified teaches a thin film transistor as set forth in claim 3 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the first channel part and the second channel part are non-conductorized parts of the active layer (130) (see Lee, Fig.3 as shown above).
Regarding Claim 5: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein each of the first channel part and the second channel part extends from the first connection portion to the second connection portion (see Lee, Fig.3 as shown above).
Regarding Claim 6: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the second channel part is parallel to a longitudinal direction of the channel portion (see Lee, Fig.3 as shown above), and
wherein the longitudinal direction of the channel portion is defined as a direction parallel to a direction connecting the first connection portion and the second connection portion (see Lee, Fig.3 as shown above).
Regarding Claim 7: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein a width of the second channel part is in a range of 10% to 50% with respect to a width of the channel portion (see Lee, Fig.3 as shown above), and
wherein the width of the second channel part is defined as a distance between both ends of the second channel part measured in a direction perpendicular to a length direction of the channel portion (see Lee, Fig.3 as shown above).
In addition, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of the second channel part through routine experimentation and optimization to obtain optimal or desired device performance because the width of the second channel part is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 8: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein an area of the second active layer (132) disposed in the second channel part is in a range of 50% or less with respect to a total area of the second channel part (see Lee, Figs.3-4 as shown above).
Regarding Claim 9: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the second active layer (130c) is not disposed on the second channel part (334/335) (see Yamazaki, Figs.17A-17B as shown above).
Regarding Claim 10: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein an area of the second active layer (130c) disposed in the first channel part (333) is in a range of 90% or more with respect to a total area of the first channel part (333) (see Yamazaki, Figs.17A-17B as shown above).
Regarding Claim 11: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the second active layer (130c) is disposed in an entire region of the first channel part, in a plan view (see Yamazaki, Figs.17A-17B as shown above).
Regarding Claim 12: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the active layer (130) further includes a third active layer (130c) on the second active layer (130b) (see Yamazaki, Figs.17A-17B as shown above), and
wherein at least a part of the third active layer (130c) is disposed in the first channel part (333) (see Yamazaki, Figs.17A-17B as shown above).
Regarding Claim 13: Yamazaki as modified teaches a thin film transistor as set forth in claim 12 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the third active layer is not disposed in the second channel part (see Lee, Figs.3 and 4 as shown above).
Regarding Claim 14: Yamazaki as modified teaches a thin film transistor as set forth in claim 12 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the third active layer (130c) is disposed in both the first channel part (333) and the second channel part (333) (see Yamazaki, Figs.13A-13B).
Regarding Claim 19: Yamazaki discloses a display apparatus (see Yamazaki, Figs.17A-17B as shown above, Fig.22, and ¶ [0002]) comprising:
a pixel driving circuit (see Yamazaki, Figs.17A-17B as shown above, Fig.22, ¶ [0283], and ¶ [0283]- ¶ [0289]); and
a display element electrically connected to the pixel driving circuit (see Yamazaki, Figs.17A-17B as shown above, Fig.22, ¶ [0283], and ¶ [0283]- ¶ [0289]);
wherein the pixel driving circuit includes a thin film transistor (see Yamazaki, Figs.17A-17B as shown above, Fig.22, ¶ [0283], and ¶ [0283]- ¶ [0289]) including:
an active layer (130) (see Yamazaki, Figs.17A-17B as shown above); and
a gate electrode (170) partially overlapping the active layer (130) (see Yamazaki, Figs.17A-17B as shown above);
wherein the active layer (130) includes:
a channel portion (a portion of active layer 130 which overlaps the gate electrode 170) (see Yamazaki, Figs.17A-17B as shown above);
a first connection portion (a portion of active layer 130 which does not overlaps the gate electrode 170) at a first side of the channel portion (a portion of active layer 130 which overlaps the gate electrode 170) (see Yamazaki, Figs.17A-17B as shown above); and
a second connection portion (a portion of active layer 130 which does not overlaps the gate electrode 170) at a second side of the channel portion (a portion of active layer 130 which overlaps the gate electrode 170), the second connection portion spaced apart from the first connection portion (see Yamazaki, Figs.17A-17B as shown above);
wherein the channel portion (a portion of active layer 130 which overlaps the gate electrode 170) includes:
a first channel part (333) overlapping the gate electrode (170) (see Yamazaki, Figs.17A-17B as shown above); and
wherein the active layer (130) includes:
a first active layer (130a/130b) (see Yamazaki, Figs.17A-17B as shown above); and
a second active layer (130c) on the first active layer (130a/130b) (see Yamazaki, Figs.17A-17B as shown above);
wherein the first channel part (333) includes the first active layer (130a/130b) and the second active layer (130c) (see Yamazaki, Figs.17A-17B as shown above),
wherein the channel portion (a portion of active layer 130 which overlaps the gate electrode 170), the first connection portion and the second connection portion are integrally formed (see Yamazaki, Figs.17A-17B as shown above).
Yamazaki is silent upon explicitly disclosing wherein a second channel part not overlapping the gate electrode;
wherein the second channel part includes the first active layer;
wherein the first channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion, and
wherein the second channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion.
For support see Lee, which teaches wherein the channel portion (130) (see Lee, Figs.3 and 4 as shown above and ¶ [0004]) includes:
a second channel part not overlapping the gate electrode (110) (see Lee, Fig.3 as shown above and ¶ [0004]);
wherein the second channel part includes the first active layer (131) (see Lee, Fig.3 as shown above and ¶ [0004]);
wherein the first channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion (see Lee, Fig.3 as shown above and ¶ [0004]), and
wherein the second channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion (see Lee, Fig.3 as shown above and ¶ [0004]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki and Lee to form the configurations of Yamazaki’s thin film transistor according to the teachings of Lee thin film transistor configuration in order to obtain a thin film transistor capable of improving stability and performance.
The combination of Yamazaki and Lee is silent upon explicitly disclosing wherein the second active layer includes a material having greater mobility than the first active layer.
For support see Zhang, which teaches wherein the second active layer (5) includes a material having greater mobility than the first active layer (4) (see Zhang, Fig.9, ¶ [0045], and ¶ [0068]- ¶ [0072]).
The combination of Yamazaki and Lee teaches the claimed invention except for the material of the second active layer. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki, Lee, and Zhang to enable the second active layer includes a material having greater mobility than the first active layer as taught by Zhang in order to obtain the display substrate with a narrow bezel, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Regarding Claim 20: Yamazaki as modified teaches a display apparatus as set forth in claim 19 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the thin film transistor is a driving transistor electrically connected to the display element and is configured to drive the display element (see Yamazaki, Figs.17A-17B as shown above and Fig.22).
Claim(s) 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (U.S. 2015/0221774 A1, hereinafter refer to Yamazaki), Lee et al. (U.S. 2022/0157997 A1, hereinafter refer to Lee), and Zhang et al. (U.S. 2021/0135144 A1, hereinafter refer to Zhang) as applied to claim 1 above, and further in view of Kubota et al. (JP 2010171163 A1, hereinafter refer to Kubota).
JP 2010171163 A (hereinafter refer to Kubota) is relied upon solely for the English language translation of JP 2010171163 A.
Regarding Claim 15: Yamazaki as modified teaches a thin film transistor as applied to claim 1 above. The combination of Yamazaki and Zhang is silent upon explicitly disclosing wherein the gate electrode includes a plurality of protrusion parts spaced apart from each other in a plan view, and
wherein the second channel part is disposed between adjacent protrusion parts of the gate electrode.
For support see Kubota, which teaches wherein the gate electrode (105) includes a plurality of protrusion parts spaced apart from each other in a plan view (see Kubota, Figs.3-5 and page.3), and
wherein the second channel part (103) is disposed between adjacent protrusion parts of the gate electrode (105) (see Kubota, Figs.3-5 and page.3).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki, Lee, Zhang, and Kubota to enable the known configuration of the gate electrode and channel region as taught by Kubota in order to suppress generation of carriers in the depletion layer and reduce the leakage current due to the defect level located at the channel end.
Regarding Claim 16: Yamazaki as modified teaches a thin film transistor as set forth in claim 15 as above. The combination of Yamazaki, Lee, Zhang, and Kubota further teaches wherein the plurality of protrusion parts protrudes in a width direction of the channel portion (see Kubota, Figs.3-5), and
wherein a width direction of the channel portion is defined in a direction perpendicular to a direction connecting the first connection portion (106) and the second connection portion (106) (see Kubota, Figs.3-5).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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