Prosecution Insights
Last updated: October 02, 2026
Application No. 18/454,273

THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS COMPRISING THE SAME

Non-Final OA §103
Filed
Aug 23, 2023
Priority
Dec 29, 2022 — RE 10-2022-0188532
Examiner
DINKE, BITEW A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
3 (Non-Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
572 granted / 785 resolved
+4.9% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
56 currently pending
Career history
816
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
65.8%
+25.8% vs TC avg
§102
8.1%
-31.9% vs TC avg
§112
11.8%
-28.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 785 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/09/2026 has been entered. Response to Arguments Applicant's arguments filed 07/09/2026 have been fully considered but they are not persuasive. The Applicant argues that in regard to claims 1 and 19 that the combination of Yamazaki, Lee, and Zhang prior art, does not teach the limitation of “a source electrode connected to the active layer; and a drain electrode spaced apart from the source electrode and connected to the active layer; wherein the second active layer is disposed directly on an upper surface of the first active layer and forms a main channel of the first channel part, wherein the second channel part includes the first active layer and is free of the second active layer, and the second channel part does not overlap the source electrode and the drain electrode.” In response to this argument, the Examiner directs the applicant’s attention to the combination of Yamazaki, Lee, and Zhang prior art, which clearly teaches the limitation of as follows: Yamazaki teaches a source electrode (140) connected to the active layer (130) (see Yamazaki, Figs.17A-17B as shown below); and a drain electrode (150) spaced apart from the source electrode (130) and connected to the active layer (130) (see Yamazaki, Figs.17A-17B as shown below); wherein the second active layer (130c) is disposed directly on an upper surface of the first active layer (130a/130b) and forms a main channel of the first channel part (see Yamazaki, Figs.17A-17B as shown below), wherein the second channel part (335) includes the first active layer (130a/130b) and is free of the second active layer (130c), and the second channel part (335) does not overlap the source electrode (140) and the drain electrode (150) (see Yamazaki, Figs.17A-17B as shown below). In addition, during patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). While the claims of issued patents are interpreted in light of the specification, prosecution history, prior art and other claims, this is not the mode of claim interpretation to be applied during examination. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004) (The USPTO uses a different standard for construing claims than that used by district courts; during examination the USPTO must give claims their broadest reasonable interpretation.) This means that the words of the claim must be given their plain meaning unless applicant has provided a clear definition in the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) >; Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004). The Examiner would further point out that “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). Therefore, the combination of Yamazaki, Lee, and Zhang prior art reference does meet all the limitation in claims 1 and 19. Allowable Subject Matter Claims 24 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the gate electrode includes a plurality of protrusion parts spaced apart from each other in a plan view, wherein the second channel part is defined in an area disposed between adjacent protrusion parts of the gate electrode, wherein the plurality of protrusion parts protrudes in a width direction of the channel portion, and wherein a width direction of the channel portion is defined in a direction perpendicular to a direction connecting the first connection portion and the second connection portion,” as recited in claim 24. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-7, 10-14 and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (U.S. 2015/0221774 A1, hereinafter refer to Yamazaki) in view of Lee et al. (U.S. 2022/0157997 A1, hereinafter refer to Lee) and Zhang et al. (U.S. 2021/0135144 A1, hereinafter refer to Zhang). Regarding Claim 1: Yamazaki discloses thin film transistor (see Yamazaki, Figs.17A-17B as shown below and ¶ [0002]) comprising: PNG media_image1.png 296 470 media_image1.png Greyscale PNG media_image2.png 413 502 media_image2.png Greyscale an active layer (130) (see Yamazaki, Figs.17A-17B as shown above); a gate electrode (170) partially overlapping the active layer (130) (see Yamazaki, Figs.17A-17B as shown above); a source electrode (140) connected to the active layer (130) (see Yamazaki, Figs.17A-17B as shown above); and a drain electrode (150) spaced apart from the source electrode (130) and connected to the active layer (130) (see Yamazaki, Figs.17A-17B as shown above); wherein the active layer (130) includes: a channel portion (333/335) (see Yamazaki, Figs.17A-17B as shown above); a first connection portion (331) at a first side of the channel portion (333/335) (see Yamazaki, Figs.17A-17B as shown above); and a second connection portion (332) at a second side of the channel portion (333/335), the second connection portion (332) being spaced apart from the first connection portion (331) (see Yamazaki, Figs.17A-17B as shown above); wherein the channel portion (333/335) includes: a first channel part (333) overlapping the gate electrode (170) (see Yamazaki, Figs.17A-17B as shown above); and a second channel part (335) not overlapping the gate electrode (170) (see Yamazaki, Figs.17A-17B as shown above); wherein the active layer (130) includes: a first active layer (130a/130b) (see Yamazaki, Figs.17A-17B as shown above); and a second active layer (130c) on the first active layer (130a/130b) (see Yamazaki, Figs.17A-17B as shown above); wherein the second active layer (130c) is disposed directly on an upper surface of the first active layer (130a/130b) and forms a main channel of the first channel part (see Yamazaki, Figs.17A-17B as shown above), wherein the first channel part (333) includes the first active layer (130a/130b) and the second active layer (130c) (see Yamazaki, Figs.17A-17B as shown above); wherein the second channel part (335) includes the first active layer (130a/130b) and is free of the second active layer (130c), and the second channel part (335) does not overlap the source electrode (140) and the drain electrode (150) (see Yamazaki, Figs.17A-17B as shown above), wherein the channel portion (a portion of active layer 130 which overlaps the gate electrode 170), the first connection portion and the second connection portion are integrally formed (see Yamazaki, Figs.17A-17B as shown above). Yamazaki is silent upon explicitly disclosing wherein the first channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion, and wherein the second channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion. For support see Lee, which teaches wherein the first channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion (see Lee, Fig.3 as shown below and ¶ [0004]), and wherein the second channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion (see Lee, Fig.3 as shown below and ¶ [0004]). PNG media_image3.png 722 953 media_image3.png Greyscale PNG media_image4.png 577 693 media_image4.png Greyscale Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki and Lee the Yamazaki’s first channel part and second channel part to be formed between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion in plan view, as taught by Lee in order to obtain a thin film transistor capable of improving stability and performance. The combination of Yamazaki and Lee is silent upon explicitly disclosing wherein the second active layer includes a material having greater mobility than the first active layer. For support see Zhang, which teaches wherein the second active layer (5) includes a material having greater mobility than the first active layer (4) (see Zhang, Fig.9, ¶ [0045], and ¶ [0068]- ¶ [0072]). The combination of Yamazaki and Lee teaches the claimed invention except for the material of the second active layer. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki, Lee, and Zhang to enable the second active layer includes a material having greater mobility than the first active layer as taught by Zhang in order to obtain the display substrate with a narrow bezel, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416. Regarding Claim 2: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the second channel part is configured to be driven by a fringing electric field generated by the gate electrode (110) (see Lee, Fig.3 as shown above). Note: the discovery of a previously unappreciated property of the combination of Yamazaki, Lee, and Zhang prior art composition, or of a scientific explanation for the combination of Yamazaki, Lee, and Zhang prior art’s functioning, does not render the old composition patentably new to the discoverer. Regarding Claim 3: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the active layer (130) is an oxide semiconductor layer including an oxide semiconductor material (see Yamazaki, Figs.17A-17B as shown above), and wherein each of the first connection portion (331/332) and the second connection portion (331/332) is formed by selective conductorization of the oxide semiconductor layer (see Yamazaki, Figs.17A-17B as shown above). Note: patentability of a product does not depend on its method of production. Regarding Claim 4: Yamazaki as modified teaches a thin film transistor as set forth in claim 3 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the first channel part and the second channel part are non-conductorized parts of the active layer (130) (see Lee, Fig.3 as shown above). Regarding Claim 5: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein each of the first channel part and the second channel part extends from the first connection portion to the second connection portion (see Lee, Fig.3 as shown above). Regarding Claim 6: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the second channel part is parallel to a longitudinal direction of the channel portion (see Lee, Fig.3 as shown above), and wherein the longitudinal direction of the channel portion is defined as a direction parallel to a direction connecting the first connection portion and the second connection portion (see Lee, Fig.3 as shown above). Regarding Claim 7: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein a width of the second channel part is in a range of 10% to 50% with respect to a width of the channel portion (see Lee, Fig.3 as shown above), and wherein the width of the second channel part is defined as a distance between both ends of the second channel part measured in a direction perpendicular to a length direction of the channel portion (see Lee, Fig.3 as shown above). In addition, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of the second channel part through routine experimentation and optimization to obtain optimal or desired device performance because the width of the second channel part is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05 Regarding Claim 10: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein an area of the second active layer (130c) disposed in the first channel part (333) is in a range of 90% or more with respect to a total area of the first channel part (333) (see Yamazaki, Figs.17A-17B as shown above). Regarding Claim 11: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the second active layer (130c) is disposed in an entire region of the first channel part, in a plan view (see Yamazaki, Figs.17A-17B as shown above). Regarding Claim 12: Yamazaki as modified teaches a thin film transistor as set forth in claim 1 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the active layer (130) further includes a third active layer (130c) on the second active layer (130b) (see Yamazaki, Figs.17A-17B as shown above), and wherein at least a part of the third active layer (130c) is disposed in the first channel part (333) (see Yamazaki, Figs.17A-17B as shown above). Regarding Claim 13: Yamazaki as modified teaches a thin film transistor as set forth in claim 12 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the third active layer is not disposed in the second channel part (see Lee, Figs.3 and 4 as shown above). Regarding Claim 14: Yamazaki as modified teaches a thin film transistor as set forth in claim 12 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the third active layer (130c) is disposed in both the first channel part (333) and the second channel part (335) (see Yamazaki, Figs.13A-13B). Regarding Claim 19: Yamazaki discloses a display apparatus (see Yamazaki, Figs.17A-17B as shown above, Fig.22, and ¶ [0002]) comprising: a pixel driving circuit (see Yamazaki, Figs.17A-17B as shown above, Fig.22, ¶ [0283], and ¶ [0283]- ¶ [0289]); a display element electrically connected to the pixel driving circuit (see Yamazaki, Figs.17A-17B as shown above, Fig.22, ¶ [0283], and ¶ [0283]- ¶ [0289]); a source electrode (140) connected to an active layer (130) (see Yamazaki, Figs.17A-17B as shown above); and a drain electrode (150) spaced apart from the source electrode (140) and connected to the active layer (130) (see Yamazaki, Figs.17A-17B as shown above); wherein the pixel driving circuit includes a thin film transistor (see Yamazaki, Figs.17A-17B as shown above, Fig.22, ¶ [0283], and ¶ [0283]- ¶ [0289]) including: an active layer (130) (see Yamazaki, Figs.17A-17B as shown above); and a gate electrode (170) partially overlapping the active layer (130) (see Yamazaki, Figs.17A-17B as shown above); wherein the active layer (130) includes: a channel portion (333/335) (see Yamazaki, Figs.17A-17B as shown above); a first connection portion (331) at a first side of the channel portion (333/335) (see Yamazaki, Figs.17A-17B as shown above); and a second connection portion (332) at a second side of the channel portion (333/335), the second connection portion (332) spaced apart from the first connection portion (331) (see Yamazaki, Figs.17A-17B as shown above); wherein the channel portion (333/335) includes: a first channel part (333) overlapping the gate electrode (170) (see Yamazaki, Figs.17A-17B as shown above); and a second channel part (335) not overlapping the gate electrode (170) (see Yamazaki, Figs.17A-17B as shown above); wherein the active layer (130) includes: a first active layer (130a/130b) (see Yamazaki, Figs.17A-17B as shown above); and a second active layer (130c) on the first active layer (130a/130b) (see Yamazaki, Figs.17A-17B as shown above); wherein the second active layer (130c) is disposed directly on an upper surface of the first active layer (130a/130b) and forms a main channel of the first channel part (333) (see Yamazaki, Figs.17A-17B as shown above), wherein the first channel part (333) includes the first active layer (130a/130b) and the second active layer (130c) (see Yamazaki, Figs.17A-17B as shown above), wherein the second channel part (335) includes the first active layer (130a/130b) and is free of the second active layer (130c), and the second channel part (335) does not overlap the source electrode (140) and the drain electrode (150) (see Yamazaki, Figs.17A-17B as shown above), wherein the channel portion (333/335), the first connection portion and the second connection portion are integrally formed (see Yamazaki, Figs.17A-17B as shown above). Yamazaki is silent upon explicitly disclosing wherein the first channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion, and wherein the second channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion. For support see Lee, which teaches wherein the first channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion (see Lee, Fig.3 as shown above and ¶ [0004]), and wherein the second channel part is between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion (see Lee, Fig.3 as shown above and ¶ [0004]). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki and Lee the Yamazaki’s first channel part and second channel part to be formed between the first connection portion and the second connection portion and contacts both the first connection portion and the second connection portion in plan view, as taught by Lee in order to obtain a thin film transistor capable of improving stability and performance. The combination of Yamazaki and Lee is silent upon explicitly disclosing wherein the second active layer includes a material having greater mobility than the first active layer. For support see Zhang, which teaches wherein the second active layer (5) includes a material having greater mobility than the first active layer (4) (see Zhang, Fig.9, ¶ [0045], and ¶ [0068]- ¶ [0072]). The combination of Yamazaki and Lee teaches the claimed invention except for the material of the second active layer. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki, Lee, and Zhang to enable the second active layer includes a material having greater mobility than the first active layer as taught by Zhang in order to obtain the display substrate with a narrow bezel, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416. Regarding Claim 20: Yamazaki as modified teaches a display apparatus as set forth in claim 19 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the thin film transistor is a driving transistor electrically connected to the display element and is configured to drive the display element (see Yamazaki, Figs.17A-17B as shown above and Fig.22). Regarding Claim 21: Yamazaki as modified teaches a display apparatus as set forth in claim 19 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the second channel part (335) is configured to be driven by a fringing electric field generated by the gate electrode (170) (see Yamazaki, Figs.17A-17B as shown above). Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus.” Regarding Claim 22: Yamazaki as modified teaches a display apparatus as set forth in claim 19 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the active layer (130) is an oxide semiconductor layer including an oxide semiconductor material (see Yamazaki, Figs.17A-17B as shown above), wherein each of the first connection portion (331) and the second connection portion (332) is formed by selective conductorization of the oxide semiconductor layer (see Yamazaki, Figs.17A-17B as shown above), and wherein the first channel part (333) and the second channel part (335) are non-conductorized parts of the active layer (see Yamazaki, Figs.17A-17B as shown above). Note: patentability of a product does not depend on its method of production. Regarding Claim 23: Yamazaki as modified teaches a display apparatus as set forth in claim 19 as above. The combination of Yamazaki, Lee, and Zhang further teaches wherein the second channel part (335) is parallel to a longitudinal direction of the channel portion (333/335) (see Yamazaki, Figs.17A-17B as shown above), wherein the longitudinal direction of the channel portion (333/335) is defined as a direction parallel to a direction connecting the first connection portion (331) and the second connection portion (332) (see Yamazaki, Figs.17A-17B as shown above), and wherein a width of the second channel part (335) is in a range of 10% to 50% with respect to a width of the channel portion (333/335) (see Yamazaki, Figs.17A-17B as shown above), and wherein the width of the second channel part (335) is defined as a distance between both ends of the second channel part (335) measured in a direction perpendicular to a length direction of the channel portion (333/335) (see Yamazaki, Figs.17A-17B as shown above). In addition, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of the second channel part through routine experimentation and optimization to obtain optimal or desired device performance because the width of the second channel part is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05 Claim(s) 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (U.S. 2015/0221774 A1, hereinafter refer to Yamazaki), Lee et al. (U.S. 2022/0157997 A1, hereinafter refer to Lee), and Zhang et al. (U.S. 2021/0135144 A1, hereinafter refer to Zhang) as applied to claim 1 above, and further in view of Kubota et al. (JP 2010171163 A1, hereinafter refer to Kubota). JP 2010171163 A (hereinafter refer to Kubota) is relied upon solely for the English language translation of JP 2010171163 A. Regarding Claim 15: Yamazaki as modified teaches a thin film transistor as applied to claim 1 above. The combination of Yamazaki and Zhang is silent upon explicitly disclosing wherein the gate electrode includes a plurality of protrusion parts spaced apart from each other in a plan view, and wherein the second channel part is defined in an area disposed between adjacent protrusion parts of the gate electrode. For support see Kubota, which teaches wherein the gate electrode (105) includes a plurality of protrusion parts spaced apart from each other in a plan view (see Kubota, Figs.3-5 and page.3), and wherein the second channel part (103) is defined in an area disposed between adjacent protrusion parts of the gate electrode (105) (see Kubota, Figs.3-5 and page.3). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yamazaki, Lee, Zhang, and Kubota to enable the known configuration of the gate electrode and channel region as taught by Kubota in order to suppress generation of carriers in the depletion layer and reduce the leakage current due to the defect level located at the channel end. Regarding Claim 16: Yamazaki as modified teaches a thin film transistor as set forth in claim 15 as above. The combination of Yamazaki, Lee, Zhang, and Kubota further teaches wherein the plurality of protrusion parts protrudes in a width direction of the channel portion (see Kubota, Figs.3-5), and wherein a width direction of the channel portion is defined in a direction perpendicular to a direction connecting the first connection portion (106) and the second connection portion (106) (see Kubota, Figs.3-5). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BITEW A DINKE/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Show 3 earlier events
Mar 04, 2026
Interview Requested
Mar 11, 2026
Applicant Interview (Telephonic)
Mar 11, 2026
Examiner Interview Summary
Mar 17, 2026
Response Filed
Apr 14, 2026
Final Rejection mailed — §103
Jul 09, 2026
Request for Continued Examination
Jul 14, 2026
Response after Non-Final Action
Aug 07, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
85%
With Interview (+12.4%)
2y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 785 resolved cases by this examiner. Grant probability derived from career allowance rate.

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