DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions & Claims’ Status
Applicant’s election without traverse of Species 1 (FIG. 1) in the reply filed on 3/4/2026 is acknowledged.
Claims 4-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/4/2026.
Claims 1-19 are currently pending, with Claims 4-6 withdrawn from further consideration due to restriction requirement (see above). No claims have been amended, cancelled, or newly added.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 8/23/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE WITH CONTROL ELECTRODES AND INTERCONNECT REGIONS
Claim Objections
Claims 7 and 12 are objected to because of the following informalities:
Re Claim 7, lines 2-3 mention “the second interconnect region” when “a second interconnect region” was not previously established (improper antecedent basis). For the purposes of examination, “the second interconnect region” will be interpreted to mean “a second interconnect region”.
Re Claim 7 and 12, both claims refer to “the direction intersecting the first direction” in lines 5-6 of both claims, where it is unclear which “a direction intersecting the first direction” of Claim 1 (in lines 62-63 and again in line 72) “the” is referring to. For the purposes of examination, “the direction intersecting the first direction” will be interpreted as “a direction intersecting the first direction”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 7, 11-14, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tamaki et al (US 2019/0296132 A1, hereafter Tamaki) in view of Suwa et al (US 2021/0296495 A1, hereafter Suwa).
Re Claim 1, Tamaki discloses a semiconductor device (FIG. 1, with reference to FIGS. 2, 3A, 3B; [0028]-[0067]) comprising:
a first electrode (31; [0028]);
a second electrode (32; [0028]), at least a portion of the second electrode (32) being disposed in an element region (R1, R2, excluding interconnect regions, hereafter referred to as just R1, R2; [0031]), a direction from the first electrode (31) toward the second electrode (32) being along a first direction (Z-direction; [0028]);
a first interconnect (34; [0030]) disposed in a first interconnect region (region with W1, see FIG. 3A, hereafter referred to as just W1+; [0062]), a direction (X-direction) from the element region (R1, R2) toward the first interconnect region (W1+) being along a second direction (X-direction) intersecting the first direction (Z-direction; [0030]);
a semiconductor layer (1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14; [0028]) provided between the first electrode (31) and the second electrode (32; [0028]) and between the first electrode (31) and the first interconnect (34; [0030]), the semiconductor layer (1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14) including
a first semiconductor region (7; [0028]) electrically connected to the second electrode (32; [0028], through 14), the first semiconductor region (7) being of a first conductivity-type (p-type; [0028]), a direction (Z-direction) from the first electrode (31) toward the first semiconductor region (7) being along the first direction (Z-direction; [0028]), the first semiconductor region (7) including a first semiconductor portion (7 under 34, see FIG. 3A; [0030]) disposed in the first interconnect region (W1+; [0030]) and a second semiconductor portion (7 not under 34, see FIG. 3A; [0030]) disposed in the element region (R1, R2; [0028]),
a second semiconductor region (5; [0028]) provided between the first electrode (31) and the first semiconductor region (7; [0030]), the second semiconductor region (5) being of a second conductivity-type (n-type; [0028]),
a third semiconductor region (4; [0028]) provided between the first electrode (31) and the second semiconductor region (5; [0028]), the third semiconductor region (4) being of the first conductivity-type (p-type; [0028]),
a fourth semiconductor region (2; [0028]) provided between the first electrode (31) and the second semiconductor region (5; [0028]), the fourth semiconductor region (2) being of the second conductivity-type (n-type; [0028]), an impurity concentration of the second conductivity-type (n-type) in the fourth semiconductor region (2) being higher than an impurity concentration of the second conductivity-type (n-type) in the second semiconductor region (5; [0028], n vs. n-),
a fifth semiconductor region (14; [0028]) disposed in the first interconnect region (W1+; [0030], at least in part), the fifth semiconductor region (14) being electrically connected to the second electrode (32; [0028]), the fifth semiconductor region (14) being of the first conductivity-type (p-type; [0028]), at least a portion of the first semiconductor portion (7 under 34) being between the second semiconductor region (5) and the fifth semiconductor region (14; [0030]), an impurity concentration of the first conductivity-type (p-type) in the fifth semiconductor region (14) being higher than an impurity concentration of the first conductivity-type (p-type) in the first semiconductor region (7; [0028], p+ vs. p),
a sixth semiconductor region (8.L, see FIG. Z1 below; [0028]) disposed in the first interconnect region (W1+; [0030]), the sixth semiconductor region (8.L) being electrically connected to the second electrode (32; [0028]), the sixth semiconductor region (8.L) being of the second conductivity-type (n-type; [0028]), at least a portion of the first semiconductor portion (7 under 34) being between the second semiconductor region (5) and the sixth semiconductor region (8.L; [0030]), and
a seventh semiconductor region (8.R, see FIG. Z1 below; [0028]) disposed in the element region (R1, R2; [0028]), the seventh semiconductor region (8.R) being electrically connected to the second electrode (32; [0028]), the seventh semiconductor region (8.R) being of the second conductivity-type (n-type; [0028]), a portion of the second semiconductor portion (7 not under 34) being between the second semiconductor region (5) and the seventh semiconductor region (8.R; [0028]);
a first control electrode (20; [0028]) facing the first semiconductor region (7) and the second semiconductor region (5) via a first insulating portion (21; [0037]), the first control electrode (20) being arranged with the first semiconductor region (7) and the second semiconductor region (5) in a direction (Y-direction) intersecting the first direction (Z-direction; [0028]), the first control electrode (20) including a first interconnect region portion (28; [0039]) disposed in the first interconnect region (W1+; [0039]), the first interconnect region portion (28) being electrically connected to the first interconnect (34; [0039]).
Tamaki does not explicitly disclose a second control electrode facing the first semiconductor region (7), the second semiconductor region (5), and the seventh semiconductor region (8.R) via a second insulating portion, the second control electrode being arranged with the first semiconductor region (7), the second semiconductor region (5), and the seventh semiconductor region (8.R) in a direction intersecting the first direction (Z-direction), the second control electrode being insulated from the first interconnect (34).
However, Suwa discloses a semiconductor device (FIG.1, with reference to FIGS. 2A, 2B, 2C) comprising a second control electrode (60; [0020]) facing the first semiconductor region (13; [0028]) and the second semiconductor region (11; [0027]) via a second insulating portion (65, see FIG. 2B, internal portion; [0024]), the second control electrode (60) being arranged with the first semiconductor region (13) and the second semiconductor region (11) in a direction (Y-direction) intersecting the first direction (Z-direction, see FIG. 2B; [0034]), the second control electrode (20) being insulated from the first interconnect (33; [0035]).
While Suwa does not teach an analogous seventh semiconductor region, in combination the remaining limitation would be met because Tamaki’s seventh semiconductor region (Tamaki: 8.R) would face and be arranged with the second control electrode (Suwa: 60) due to the second control electrode taking up the same vertical footprint as Tamaki’s first control electrode (Tamaki: 20, at least in comparison to the rightmost end portion shown in FIG. 2B of Tamaki).
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Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Tamaki with the limitations taught by Suwa to utilize a second control electrode (Suwa: 60) underneath the first control electrode (Tamaki: 20) to reduce the turn-off loss by shortening the time necessary to deplete the n-type base layer (Tamaki: 5) as taught by Suwa ([0057]).
FIG. Z1: Annotated version of Tamaki FIG. 3A
Re Claim 2, Tamaki and Suwa teach the device according to Claim 1, while Tamaki further teaches the device comprises:
a first contact region (c1, see FIG. Z1 above, interface ; [0038]) electrically connecting the second electrode (32) and at least one of the fifth semiconductor region (14; [0038]) and the sixth semiconductor region (8.L; [0038]) in the first interconnect region (W1+; [0038]); and
a second contact region (c2, see FIG. Z1 above, a region between insulating layer; [0038]) electrically connecting the second electrode (32) and the first semiconductor region (7) in the element region (R1, R2; [0038]).
Re Claim 7, Tamaki and Suwa teach the device according to Claim 1, while Suwa further teaches the device comprises:
a second interconnect (37; [0035]) disposed in the second interconnect region (area below 37; [0035]),
a direction (Y-direction) from the element region (area below 30; [0036]) toward the second interconnect region (area below 37) being along the direction (Y-direction) intersecting the first direction (Z-direction; [0035]),
a portion of the semiconductor layer (11; [0027]) being provided between the first electrode (20; [0027]) and the second interconnect (37; [0035]),
the second control electrode (60) being electrically connected to the second interconnect (37) in the second interconnect region (area below 37; [0035]), and
the first control electrode (40; [0037]) being insulated from the second interconnect (37; [0037], by 65).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Tamaki with the limitations taught by Suwa to utilize a second interconnect (Suwa: 37) along with the second control electrode (Suwa: 60) to reduce the turn-off loss by shortening the time necessary to deplete the n-type base layer (Tamaki: 5) as taught by Suwa ([0057]).
Re Claim 11, Tamaki and Suwa teach the device according to Claim 1, while Suwa further teaches the device comprises:
a first electrode pad (first of “gate pads”; [0041]) electrically connected to the first control electrode (40) and insulated from the second control electrode (60; [0041], by nature of different gate voltages being able to be applied); and
a second electrode pad (second of “gate pads”; [0041]) electrically connected to the second control electrode (60) and insulated from the first control electrode (40; [0041], by nature of different gate voltages being able to be applied).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Tamaki with the limitations taught by Suwa to utilize insulated electrode pads (Suwa: “gate pads”) to regulate the flow of current as taught by Suwa ([0041]).
Re Claim 12, Tamaki and Suwa teach the device according to Claim 1, while Tamaki further teaches the device comprises:
a conductive member (25) facing the first semiconductor region (7) and the second semiconductor region (5) via a third insulating portion (26; [0036]) and arranged with the first semiconductor region (7) and the second semiconductor region (5) in the direction (Y-direction) intersecting the first direction (Z-direction; [0036], see FIG. 1), wherein
the conductive member (25) is electrically connected to the second electrode (32) in the element region (R1, R2; [0036]).
Re Claim 13, Tamaki and Suwa teach the device according to Claim 1, while Tamaki further teaches wherein the first control electrode (20) extends in the second direction (X-direction; [0028]).
Suwa further teaches wherein the second control electrode (60) extends in the second direction (Y-direction, which is analogous to X-direction of Tamaki; [0037]) and is arranged with the first control electrode (40; [0037]) in a third direction (X-direction, which is analogous to Y-direction of Tamaki) perpendicular to the first direction (Z-direction) and the second direction (Y-direction).
No further changes made to the combination, see Claim 1 for obviousness reasoning.
Re Claim 14, Tamaki and Suwa teach the device according to Claim 13, while Tamaki further teaches wherein
a plurality of the first control electrodes (20) are provided ([0028], see FIG. 1),
the plurality of first control electrodes (20) are arranged in the third direction (Y-direction; [0028]), and
the first interconnect (34) extends in the third direction (Y-direction, see top of FIG. 1; [0028]) and is electrically connected to the plurality of first control electrodes (20; [0028]).
Re Claim 17, Tamaki and Suwa teach the device according to Claim 1, while Suwa further teaches wherein the first control electrode (40) and the second control electrode (60) are turned on when a current flows from the second electrode (30) to the first electrode (20; [0050]-[0051]).
No further changes made to the combination, see Claim 1 for obviousness reasoning.
Re Claim 18, Tamaki and Suwa teach the device according to Claim 17, while Suwa further teaches wherein duration of an on state of the first control electrode (40) and the second control electrode (60) is 10 microseconds or more and 100 microseconds or less ([0050], timing dependent on external voltage application, so time range is inherent to the structure, see MPEP 2144.I).
No further changes made to the combination, see Claim 1 for obviousness reasoning.
Allowable Subject Matter
Claims 3, 8-10, 15-16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 3, the prior art cannot anticipate, or render obvious, the limitations of: another one of the plurality of first contact regions is in contact with the sixth semiconductor region and separated from the fifth semiconductor region, in combination with the additionally claimed features of Claim 3.
Re Claim 8, the prior art cannot anticipate, or render obvious, the limitations of: at least a portion of the eighth semiconductor region being disposed in the second interconnect region, […] at least a portion of a third semiconductor portion of the first semiconductor region disposed in the second interconnect region being between the eighth semiconductor region and the second semiconductor region, in combination with the additionally claimed features of Claim 8.
Re Claim 15, the prior art cannot anticipate, or render obvious, the limitations of: wherein the first control electrode is turned off before the second control electrode is turned off, in combination with the additionally claimed features of Claim 15.
In Re Claims 9-10 and Claims 16, 19, they are objected to due to their dependence from Claims 8 and 15, respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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