DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because it describes a semiconductor device, rather than a method of manufacturing a semiconductor device, to which the claims are directed. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention, “SEMICONDUCTOR DEVICE WITH TRENCH STRUCTURES AND METHOD FOR MANUFACTURING SAME” is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH TRENCH STRUCTURES.”
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because:
reference characters “104104”, "10304", and “104” have all been used to designate a single layer in figure 2, and there are similar labeling errors in figures 6E and 6F’
in figure 2 there are illegible extraneous marks following one of the labels of layer 103;
figures 3, 4, 8C, 8D and 8E have overlapping illegible labels.
Please review all drawings and check that all labels are legible and correct.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 8 is objected to because of the following informalities: “and reaches to the silicon carbide substrate” should be: “and reaches the silicon carbide substrate.” Appropriate correction is required.
Claim 29 is objected to because of the following informalities: claim 29 recites the limitation "the SiC substrate". There is insufficient antecedent basis for this limitation. Appropriate correction is required
Claim 31 is objected to because of the following informalities: the phrase “a SiC substrate” should be corrected to either “the SiC substrate” or “a second SiC substrate.” Appropriate correction is required.
Claim 32 is objected to because of the following informalities: claim 22 recites the limitation "the gate extension region". There is insufficient antecedent basis for this limitation. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10, 11, 12, and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, there is a lack of antecedent basis for “the second oxide layer,” which leads to ambiguity in the scope of the claim. It is unclear whether this layer is intended to be an additional second oxide layer or the second oxide layer disclosed in claim 9. If the second oxide layer disclosed in claim 9 is what is meant, then the claim dependency would have to be amended so that claim 10 was dependent on claim 9.
Regarding claim 11, there is a lack of antecedent basis for “the dielectric layer,” which leads to ambiguity in the scope of the claim. It is unclear whether this layer is intended to be an additional dielectric layer or the dielectric layer disclosed in claim 9. If the dielectric layer disclosed in claim 9 is what is meant, then the claim dependency would have to be amended so that claim 11 was dependent on claim 9.
Regarding claim 12, it is unclear whether “a plurality of mesa structures” refers to an additional plurality of mesa structures or to the plurality of mesa structures disclosed in claim 9. If this plurality of mesa structures is an additional plurality of mesa structures, then they should be referred to as “a second plurality of mesa structures” to avoid ambiguity. If this plurality of mesa structures is the same as that referenced in claim 9, then there are problems with both the antecedent basis and the claim dependency. Fixing these problems would include amending claim 12 to depend on claim 9.
“Forming a plurality of channel implantation regions in a plurality of mesa structures” is ambiguous as written. One possible interpretation of this limitation is: "forming a plurality of channel implantation regions in each of the [a] plurality of mesa structures." The wording of claim 12 should be amended to clarify this limitation.
“Forming a source region on a top surface of the mesa structures’ is likewise ambiguously worded: either one source region is on top of all the mesa structures or each mesa structure has a source region on its top surface." The wording of claim 12 should be amended to clarify this limitation.
Regarding claim 13, the phrase “a plurality of mesa structures wherein each respective mesa structure of the plurality of mesa structures is formed between the respective adjacent trench structures” is ambiguous. The same phase is recited in claim 12, therefore: if the plurality of mesa structures of claim 13 are the same as those of claim 12, the antecedent basis is incorrect; however, if this refers to a separate plurality of mesa structures, it should be called “a second plurality of mesa structures” in claim 13.
The remaining language of claim 13 is also ambiguous: “each gate extension region is formed below each source region and connected to the gate region, wherein the gate extension region is located between the connected gate region and the channel implantation region.” Here, it is not clear which of the plurality of gate regions of claim 12 is “the gate region.” The phrases “the gate extension region”, “the connected gate region”, and “the channel implant region” are ambiguous for analogous reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7, 12, and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ichikawa et al. (US 20240055258 A1), hereinafter Ichikawa.
Regarding claim 7, Ichikawa discloses a method for manufacturing semiconductor device, comprising:
providing a silicon carbide substrate (figure 1, 100; [0042]);
forming a plurality of trench structures (figure 2, elements 9a) on a surface of the silicon carbide substrate, wherein
each trench structure has sidewalls and a bottom (figure 2, 9a);
forming a first oxide layer on the sidewalls of the trench structures [0086], wherein
the first oxide layer comprises silicon dioxide [0086]; and
performing thermal oxidation treatment [0086].
Regarding claim 12, Ichikawa discloses the method of claim 7, further comprising:
forming a plurality of channel implantation regions in a plurality of mesa structures (As described in paragraph [0062], a channel region is formed in the base region (figure 2, element 6) toward the side surfaces of the respective trenches (9a) located in the mesa regions formed between the trenches) wherein
each respective mesa structure of the plurality of mesa structures is formed between the respective adjacent trench structures (The mesa structure in figure 2 is formed between the trenches 9a, which are a pair of trenches among a plurality of trenches, as illustrated by figure 1, where the line A-A shows the cross-section illustrated in figure 2. This is one of a plurality of active areas located on substrate 100, each area comprising trenches and corresponding mesa structures.);
forming a plurality of gate regions (fig. 2, elements 4a and 4b) on a top surface of the silicon carbide substrate, wherein
each gate region (figure 2, 4a and 4b) surrounds the sidewalls and the bottom of each trench structure (figure 2, 9a);
forming a source region on a top surface of the mesa structures (figure 2, element 7); and
forming a drain region on a bottom layer of the silicon carbide substrate (figure 2, element 1).
Regarding claim 13, Ichikawa discloses the method of claim 12, further comprising:
forming a plurality of gate extension regions (figure 2, comprising elements 3 and 4b) in a plurality of mesa structures (see rejection of the next limitation), wherein
each respective mesa structure of the plurality of mesa structures is formed between the respective adjacent trench structures (In the active area of figure 2, a mesa is formed between trench structures 9a, and a plurality of mesa structures exist, as illustrated by figure 1, where the active area illustrated in figure 2 is one of many active areas each of which comprise a plurality of trench structures and a corresponding plurality of mesa structures formed identically to those in figure 2.)
each gate extension region (figure 2, comprising elements 3 and 4b) is formed below each source region (figure 2, 7) and connected to the gate region (figure 3, 4b and 4d), wherein
the gate extension region (figure 2, comprising elements 3 and 4b) is located between the connected gate region (figure 3, 4b and 4d) and the channel implantation region (figure 2, layer 6).
Claim 21, 29, 31, and 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Onose et al. (US 20050218424 A1), hereinafter Onose.
Regarding claim 21, Onose discloses a method for manufacturing a semiconductor device, comprising:
forming a drain region (figure 11, 10) and a source region (figure 11, 12) in a SiC substrate [0002], wherein
the drain region (figure 11,10) adjoins a bottom of the SiC substrate (see figure 11), and
the source region is above the drain region (see figure 11, where source 11 is above drain 10);
etching a trench (figure 11, 32 – [0030] explains that the trenches are formed by etching) in the SiC substrate to form a SiC mesa structure (see the mesa formed by the trenches 32 in figure 11), wherein
the SiC mesa structure comprises a portion of the source region (figure 11 shows that the mesa between trenches 32 comprises a portion of source region 12);
forming a first oxide layer (An initial portion of the insulating oxide layer 334 is formed [0042]) on a sidewall of the SiC mesa structure, wherein the first oxide layer exposes a top surface of the SiC mesa structure and a bottom of the trench (figure 11, oxide layer 334 does not cover the bottom of the trench 35, or the top of the mesa structure 12);
after forming the first oxide layer, performing a thermal oxidation treatment to oxidize the sidewall of the SiC mesa structure to form a thermal oxide layer, wherein the thermal oxide layer is between the first oxide layer and the SiC mesa structure (Onose explains [0042] that the insulating layer (figure 11, 334) is formed by further oxidation of the sidewall (SiC) of the trench. By the nature of the process of oxidizing silicon carbide to form an insulating oxide layer, a thermal oxide layer is necessarily formed between the initial oxide layer and the silicon carbide.); and
forming a gate conductive layer on the bottom of the trench (figure 11, 23) and a source conductive layer on the top surface of the SiC mesa structure (figure 11, 221).
Regarding claim 29, Onose discloses a method for manufacturing a semiconductor device, comprising:
etching a trench (figure 11, 32 – [0030] explains that the trenches are formed by etching) in the SiC substrate to form a SiC mesa structure (see the mesas formed by the trenches 32 in figure 11),
forming a gate region (figure 11, 13) on a sidewall of the SiC mesa structure and a bottom of the trench (the formation of the gate region in the bottom and sidewalls of the mesa structure by ion implantation is described in [0018]);
after forming the gate region (figure 11, 13), forming an oxide layer (figure 11, 334) on the sidewall of the SiC mesa structure, wherein the oxide layer exposes the bottom of the trench (see figure 11, where the bottom of the trench 32 is not covered by the oxide layer 334);
after forming the first oxide layer, performing a thermal oxidation treatment to oxidize the sidewall of the SiC mesa structure to form a thermal oxide layer, wherein the thermal oxide layer is between the first oxide layer and the SiC mesa structure (Onose explains [0042] that the insulating layer (figure 11, 334) is formed by further oxidation of the sidewall (SiC) of the trench. By the nature of the process of oxidizing silicon carbide to form an insulating oxide layer, a thermal oxide layer is necessarily formed between the initial oxide layer and the silicon carbide.); and
forming a gate conductive layer (figure 11, 23) on the gate region (figure 11, 13) at the
bottom of the trench (figure 11, 32).
Regarding claim 31, Onose discloses the method of claim 29, further comprising:
forming a drain region (figure 11, 10) and a source region (figure 11, 12) in a SiC substrate [0002], wherein
the drain region (figure 11,10) adjoins a bottom of the SiC substrate (see figure 11),
the source region is above the drain region (see figure 11, where source 12 is above drain 10);
etching a trench (figure 11, 32 – [0030] explains that the trenches are formed by etching) in the SiC substrate is performed such that the SiC mesa structure (see the mesa formed by the trenches 32 in figure 11) comprises a portion of the source region (figure 11 shows that the mesa between trenches 32 comprises a portion of source region 12); and
forming a source conductive layer (221) on the portion of the source region in the SiC mesa structure (figure 11, 12).
Regarding claim 32, Onose discloses the method of claim 29, further comprising:
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forming the gate extension region in the SiC substrate (see the gate extension region indicated by the arrow on figure 11, element 334),
wherein etching the trench in the SiC substrate is performed such that the SiC mesa structure has a portion of the gate extension region (see the gate extension region portion of element 334 in figure 11, indicated by an arrow and label – the trench is etched so that a portion of the gate extension region is in the SiC mesa),
wherein forming the gate region is performed such that the gate region is connected with the gate extension region (figure 11, element 334 comprises both the gate region and the gate extension region, which are in contact.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ichikawa in view of Chiola et al. (US 20050009255 A1), hereinafter Chiola.
Regarding claim 8, Ichikawa discloses the method of manufacturing the semiconductor device of claim 7.
Ichikawa is silent regarding wherein via the thermal oxide treatment, oxygen flows through the first oxide layer and reaches the silicon carbide substrate that is connected to the first oxide layer, and the silicon carbide substrate is oxidized and forms a thermal oxide layer.
However, Chiola discloses a process for forming oxide layers wherein, via the thermal oxidation process, a thermal oxide layer is produced by oxidization of a SiC substrate surface through the silicon dioxide layer (Chiola [0024]).
It would have been obvious to a person of ordinary skill in the art before the time of filing to perform a thermal oxide treatment on the device of claim 7 to form a thermal oxide layer between the silicon dioxide layer and the silicon carbide substrate, in order to improve the adherence of the silicon dioxide layer to the trench walls (Chiola [0024]).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Ichikawa.
Regarding claim 9, Ichiwaka discloses the method of claim 7, further comprising:
forming a conductive layer by metal deposition process [0088] on the bottom of the trench structures (figure 14, 14) and on a top surface of a plurality of mesa structures (figure 14, 14), wherein
each respective mesa structure of the plurality of mesa structures is formed between the respective adjacent trench structures (see figure 14, where a mesa structure is located between each pair of the plurality of trenches: a plurality of repeating elements as in figure 14 exist, as demonstrated by figure 1);
forming an insulation layer on the dielectric layer (figure 14, 13), wherein
the insulation layer comprises borophosphosilicate glass [0052].
Ichikawa, in the embodiment illustrated by figure 14, does not explicitly disclose:
forming a second oxide layer on the first oxide layer and the conductive layer;
forming a dielectric layer on the second oxide layer.
However, Ichikawa suggests that the insulating layer 13 may comprise a stacked layer of films, including silicon dioxide, silicon nitride, and borophosphosilicate glass [0053].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to replace the borophosphosilicate glass layer 13 of Ichikawa, as illustrated in figure 14, with a layer comprising stacked layers of silicon dioxide (i.e.: a second oxide layer on the first oxide layer (11) and the conductive layer (14)), a silicon nitride dielectric layer on the silicon dioxide layer, and an insulating layer of borophosphosilicate glass, as disclosed by Ichikawa as an alternative, in order to increase the insulator layer lifetime. (L. A. Lipkin and J. W. Palmour, "Insulator investigation on SiC for improved reliability," in IEEE Transactions on Electron Devices, vol. 46, no. 3, pp. 525-532, March 1999).
Regarding claims 10 and 11, Ichikawa discloses thickness of layers in the angstrom range ([0055] and [0065], ranges less than one micrometer).
Ichikawa lacks specifically disclosing [claim 10] wherein a thickness of the second oxide layer is between 600A-1300A and [claim 11] wherein a thickness of the dielectric layer is between 1700A-2900A.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the layers of Ichikawa to have the claimed thicknesses in order to balance high-voltage blocking capability, reliability and stability, and the need to control parasitic capacitance.
Claims 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Onose in view of Shimizu (US 20110198613 A1).
Regarding claim 24, Onose discloses the method of claim 21, wherein a gate conductive layer and source conductive layer are formed.
Onose does not disclose wherein the gate conductive layer and the source conductive layer are metal silicides: Onose is silent regarding the composition of the gate conductive layer (figure 11, 23) and the source conductive layer (figure 11, 221).
However, Shimizu discloses using a metal silicide (nickel silicide [0074]) to form the gate and source conductive layers.
Therefore, it would have been obvious to a person of ordinary skill in the art before the date of filing to form gate and source contact layers of metal silicide in order to reduce the resistivity of these layers, thereby reducing the power dissipation and improving the switching efficiency of the device (K. Shenai, P. A. Piacente, C. S. Korman and B. J. Baliga, "High-performance vertical-power DMOSFETs with selectively silicided gate and source regions," in IEEE Electron Device Letters, vol. 10, no. 4, pp. 153-155, April 1989).
Regarding claim 25, Onose discloses the method of claim 21, wherein a gate conductive layer and source conductive layer are formed.
Onose does not disclose wherein forming the gate conductive layer and the source conductive layer comprises:
depositing a metal layer on the SiC substrate; and
reacting the metal layer with the top surface of the SiC mesa structure and the bottom of the trench exposed by the first oxide layer to form metal silicides.
However, Shimizu discloses depositing a metal (nickel, deposited by sputtering [0074])) on the SiC substrate in the bottom of the trench [0074]) and then reacting the metal layer (the nickel layer [0074]) with the top surface of the SiC mesa structure and the bottom of the trench exposed by the first oxide layer to form metal silicides (nickel silicide) by the process of annealing [0074].
Therefore, it would have been obvious to a person of ordinary skill in the art before the date of filing to form the gate and source electrodes by depositing a metal layer on the SiC substrate; and reacting the metal layer with the top surface of the SiC mesa structure and the bottom of the trench exposed by the first oxide layer to form metal silicides, in order to reduce the resistivity of these layers, thereby reducing the power dissipation and improving the switching efficiency of the device (Sheni et al.)
Claims 26, 27, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Onose in view of Ichikawa.
Regarding claim 26, Onose discloses the method of claim 21, further comprising: forming an insulation layer (33) on the first oxide layer and the gate conductive layer.
Onose does not teach:
forming a second oxide layer on the first oxide layer, the gate conductive layer, and the source conductive layer;
forming a nitride layer on the second oxide layer;
and forming an insulation layer on the nitride layer, wherein the insulation layer comprises borophosphosilicate glass.
However, Ichikawa teaches placing an insulating layer (comprising borophosphosilicate glass) on the source conductive layer, as well as on the first oxide layer and the gate conductive layer (figure 2, 13).
Furthermore, although Ichikawa, in the embodiment illustrated by figure 14, does not explicitly disclose:
forming a second oxide layer on the first oxide layer, the gate conductive layer, and the source conductive layer;
forming a nitride layer on the second oxide layer;
and forming an insulation layer on the nitride layer, wherein the insulation layer comprises borophosphosilicate glass,
Ichikawa suggests that the insulating layer 13 may comprise a stacked layer of films, including silicon dioxide, silicon nitride, and borophosphosilicate glass [0053].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to replace the borophosphosilicate glass layer 13 of Ichikawa, as illustrated in figure 14, with a layer comprising stacked layers of silicon dioxide (i.e.: a second oxide layer on the first oxide layer (11) and the conductive layer (14)), a silicon nitride dielectric layer on the silicon dioxide layer, and an insulating layer of borophosphosilicate glass, as disclosed by Ichikawa as an alternative, in order to increase the insulator layer lifetime. (L. A. Lipkin and J. W. Palmour, "Insulator investigation on SiC for improved reliability," in IEEE Transactions on Electron Devices, vol. 46, no. 3, pp. 525-532, March 1999).
Regarding claim 27, Onose as modified by Ichikawa discloses the method of claim 26, wherein a second oxide layer and a nitride layer are formed.
Onose, as modified by Ichikawa lacks the specific disclosure wherein a thickness of the second oxide layer is less than a thickness of the nitride layer.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the layers of Onose as modified by Ichikawa to have the claimed thickness ratio in order to increase the insulator layer lifetime (Lipkin et al.).
Regarding claim 28, Onose as modified by Ishikawa discloses the method of claim 26, wherein the second oxide layer is in contact with the first oxide layer, the gate conductive layer, and the source conductive layer (Onose figure 11 shows that the second oxide layer, part of layer 33 in figure 11, is in contact with the first oxide layer (334), the gate conductive layer (23), and the source conductive layer (comprising the layers 221 and 22).
Claims 22, 23, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Onose.
Regarding claim 22, Onose discloses the method of claim 21, wherein the thermal oxide layer and the first oxide layer are formed (comprising layer 334 of figure 11).
Onose lacks specifically disclosing wherein the thermal oxide layer has a higher density than the first oxide layer does.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, because the choice is either the thermal oxide layer has a higher density than the first oxide layer, vice versa, or they are equal, to try each of the three choices to see which one works the best in combination and it would be obvious for the user to choose wherein the thermal oxide layer has a higher density than the first oxide layer, in order to improve gate reliability.
Regarding claim 23, Onose discloses the method of claim 21, including forming the first oxide layer and an associated thermal oxide layer (comprising layer 334 of figure 11).
Onose does not explicitly disclose wherein a thickness of the thermal oxide layer is less than a thickness of the first oxide layer.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the thickness of the first oxide layer and the thermal oxide layer to have the claimed thickness ratio in order to optimize gate reliability. (R. Siemieniec et al., "A SiC Trench MOSFET concept offering improved channel mobility and high reliability," 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), Warsaw, Poland, 2017, pp. P.1-P.13).
Regarding claim 30, Onose discloses the method of claim 29, wherein the thermal oxide layer and the first oxide layer are formed (comprising layer 334 of figure 11).
Onose lacks specifically disclosing wherein the thermal oxide layer has a higher density than the first oxide layer does.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, because the choice is either the thermal oxide layer has a higher density than the first oxide layer, vice versa, or they are equal, to try each of the three choices to see which one works the best in combination and it would be obvious for the user to choose wherein the thermal oxide layer has a higher density than the first oxide layer, in order to improve gate reliability.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Onose in view of Bhalla et al. (US 20160268446 A1).
Regarding claim 33, Onose discloses the method of claim 32, further comprising: forming the gate extension region and forming the gate region (figure 11, 13), and then forming a channel implantation region (figure12, implant 1201 is then applied to form vertical channel regions 602a and 602b ) in the SiC mesa structure.
Onose lacks wherein after forming the gate extension region, and prior to forming the gate region, forming a channel implantation region in the SiC mesa structure.
Bhalla discloses first forming a gate extension region (figure 11, top gate region 605 is created with a low energy implant 1101), doped channel region (in figure 4, channel region 230 is formed by implantation 204), then the gate region is formed [0019].
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of filing to form these features in the order described by Bhalla in order to achieve improved threshold voltage control [0003].
Conclusion
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818