DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments and amendments have overcome the previous objections and 112b rejections. With regard to claim 1, it is agreed that the Onose lacks the amended limitation of “after the chemical vapor deposition process, performing thermal oxidation treatment to form a thermal oxide layer between the first oxide layer and the sidewalls of the first and second trench structures” – as can be seen in the new rejection below a new reference Seki JP2008311406A was found to teach this feature and thus a new 103 rejection was formulated.
As to independent claims 21 and 29, Applicant is correct that the newly amended feature of chemical vapor deposition is not specifically stated in Onose. As is seen in the new rejection below, Ichikawa et al. (previously cited reference) teaches this feature and thus a new 103 rejection was formulated as well as the inclusion of new reference to Seki for claim 29.
No dependent claims were specifically argued as to their merits (they were argued to not include the subject matter in the independent claims described above), therefore, they remain rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ichikawa et al. US 20240055258 in view of Seki JP2008311406A.
Regarding claim 7, Ichikawa discloses a method for manufacturing a semiconductor device, comprising:
providing a silicon carbide substrate (figure 1, 100; [0042]);
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forming first and second trench structures (figure 2, elements 9a) on a surface of the silicon carbide substrate, wherein each of the first and second trench structures has sidewalls and a bottom (see annotated figure 2);
performing a chemical vapor deposition process to form a first oxide layer on the sidewalls of the first and second trench structures, wherein the first oxide layer comprises silicon dioxide (paragraph [0086 discloses the silicon dioxide film 11is deposited by a CVD process, lining the trenches);
Ichikawa lacks after the chemical vapor deposition process, performing thermal oxidation treatment to form a thermal oxide layer between the first oxide layer and the sidewalls of the first and second trench structures.
However, Seki discloses that silicon dioxide insulating film layer 38 [0029] lines the trench (figure D), and that a thermal oxidation process is performed on this layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to use the method of Seki to form a thermal oxide layer between the first oxide layer and the sidewalls of the first and second trench structures of Ichikawa in order to improve electrical performance by creating a thermal oxide layer that has a smoother transition layer with more precisely controlled thickness.
Regarding claim 8, Ichikawa as modified by Seki discloses the method of claim 7, wherein via the thermal oxidation treatment, oxygen flows through the first oxide layer and reaches the silicon carbide substrate that is connected to the first oxide layer, and the silicon carbide substrate is oxidized and forms a thermal oxide layer (Seki in paragraph [0030] describes the formation of thermal oxidation layer wherein, via the thermal oxidation process, a thermal oxide layer is produced by oxidization of a SiC substrate surface through the silicon dioxide layer 38d, between the first oxide layer 38t and the silicon carbide substrate, as shown in figure D).
Regarding claim 9, Ichikawa as modified by Seki discloses the method of claim 7,
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wherein forming the trench structures is performed such that a mesa structure is formed between the first and second trench structures (see annotated figure 2),
and the method further comprises: forming a conductive layer by metal deposition process [0088] on the bottom of the first and second trench structures (figure 14, 14) and on a top surface of the mesa structure (figure 14, 14),
forming an insulation layer on the dielectric layer, wherein the insulation layer comprises borophosphosilicate glass (13, figure 14 is a borophosphosilicate glass film [0053]).
Ichikawa, in the embodiment illustrated by figure 14, does not explicitly disclose forming a second oxide layer on the first oxide layer and the conductive layer or forming a dielectric layer on the second oxide layer.
However, Ichikawa suggests that the insulating layer 13 may comprise a stacked layer of films, including silicon dioxide, silicon nitride, and borophosphosilicate glass [0053].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to replace the borophosphosilicate glass layer 13 of Ichikawa, as illustrated in figure 14, with a layer comprising stacked layers of silicon dioxide (i.e.: a second oxide layer on the first oxide layer (11) and the conductive layer (14)), a silicon nitride dielectric layer on the silicon dioxide layer, and an insulating layer of borophosphosilicate glass, as disclosed by Ichikawa as an alternative, in order to increase the insulator layer lifetime. (Lipkin and J. W. Palmour, "Insulator investigation on SiC for improved reliability," in IEEE Transactions on Electron Devices, vol. 46, no. 3, pp. 525-532, March 1999).
Regarding claims 10 and 11, Ichikawa as modified by Seki, as in claim 9, discloses thickness of layers in the angstrom range ([0055] and [0065], ranges less than one micrometer).
Ichikawa as modified by Seki lacks specifically disclosing [claim 10] wherein a thickness of the second oxide layer is between 600A-1300A and [claim 11] wherein a thickness of the dielectric layer is between 1700A-2900A.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner V. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the layers of Ichikawa as modified by Seki to have the claimed thicknesses in order to achieve the predictable results of balancing high-voltage blocking capability, reliability and stability, and the need to control parasitic capacitance
Regarding claim 12, Ichikawa as modified by Seki discloses the method of claim 7, wherein:
forming the trench structures is performed such that a mesa structure is formed between the first and second trench structures (trenches 9a are located so as to form the mesa region between the trenches, as illustrated in the annotated figure 2 in the rejection of claim 9), and the method further comprises:
forming a channel implantation region in the mesa structure (as described in paragraph [0062], a channel region is formed in the base region (figure 2, element 6) toward the points where the side surfaces of the respective trenches form the mesa structure),
forming first and second gate regions on a top surface of the silicon carbide substrate,
wherein each the first gate region surrounds the sidewalls and the bottom of the first -trench structure, and the second gate region surrounds the sidewalls and the bottom of the second trench structure (fig. 2, elements 4a and 4b on a top surface of the silicon carbide substrate, wherein each gate region, figure 2, 4a and 4b, surrounds the sidewalls and the bottom of each trench structure, figure 2, 9a);
forming a source region on a top surface of the mesa structure (figure 2, element 7); and
forming a drain region on a bottom layer of the silicon carbide substrate (figure 2, element 1).
Regarding claim 13, Ichikawa as modified by Seki discloses the method of claim 12, wherein
forming the trench structures is performed such that a mesa structure is formed between the first and second trench structures (In the active area of figure 2, a mesa is formed between trench structures 9a), and the method further comprises:
forming a gate extension region in the mesa structure (figure 2, the gate region comprises elements 3 and 4b), wherein
the gate extension region is formed below the source region (figure 2, 7) and connected to the first gate region (figure 3, 4b and 4d), wherein
the gate extension region (figure 2, comprising elements 3 and 4b) is located between the connected first gate region (figure 3, 4b and 4d) and the channel implantation region (figure 2, layer 6).
Claims 21-23 and 25-28 are rejected under 35 U.S.C. 103 as being unpatentable Onose et al. US 20050218424 in view of Ichikawa US 20240055258.
Regarding claim 21, Onose discloses a method for manufacturing a semiconductor device, comprising:
forming a drain region (figure 11, 10) and a source region (figure 11, 12) in a SiC substrate [0002], wherein the drain region adjoins a bottom of the SiC substrate, and the source region is above the drain region (figure 11,10 adjoins a bottom of the SiC substrate, see figure 11, and the source region is above the drain region - figure 11, where source 11 is above drain 10);
etching a trench (figure 11, 32 - [0030] explains that the trenches are formed by etching) in the SiC substrate to form a SiC mesa structure (see the mesa formed by the trenches 32 in figure 11), in the SiC substrate to form a SiC mesa structure, wherein the SiC mesa structure comprises a portion of the source region (figure 11 shows that the mesa between trenches 32 comprises a portion of source region 12);
after the chemical vapor deposition process, performing a thermal oxidation treatment to oxidize the sidewall of the SiC mesa structure to form a thermal oxide layer, wherein the thermal oxide layer is between the first oxide layer and the SiC mesa structure (Onose explains [0042] that the insulating layer (figure 11, 334) is formed by further oxidation of the sidewall (SiC) of the trench. By the nature of the process of oxidizing silicon carbide to form an insulating oxide layer, a thermal oxide layer is necessarily formed between the initial oxide layer and the silicon carbide.); and
forming a gate conductive layer on the bottom of the trench (figure 11, 23) and a source conductive layer on the top surface of the SiC mesa structure (figure 11, 221).
Onose lacks specifically performing a chemical vapor deposition process to form a first oxide layer on a sidewall of the SiC mesa structure, wherein the first oxide layer exposes a top surface of the SiC mesa structure and a bottom of the trench;
However, Ichikawa discloses [0086] that his analogous silicon dioxide film 11 is deposited by a CVD process to line similar trenches).
Therefore, it would have been obvious to a person of ordinary skill in the art before the time of filing to use the CVD process to form a first oxide layer, in order to precisely control the thickness and chemical purity of the first oxide layer.
Regarding claim 22, Onose as modified by Ichikawa discloses the method of claim 21, wherein the thermal oxide layer and the first oxide layer are formed (comprising layer 334 of figure 11).
Onose as modified by Ichikawa lacks specifically disclosing wherein the thermal oxide layer has a higher density than the first oxide layer does.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process SO scaled.' 531 F.2d at 1053, 189 USPQ at 148.). In Gardner V. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, because the choice is either the thermal oxide layer has a higher density than the first oxide layer, vice versa, or they are equal, to try each of the three choices to see which one works the best in combination, and it would be obvious for the user to choose wherein the thermal oxide layer has a higher density than the first oxide layer, in order to improve gate reliability.
Regarding claim 23, Onose as modified by Ichikawa discloses the method of claim 21, including forming the first oxide layer and an associated thermal oxide layer (comprising layer 334 of figure 11).
Onose as modified by Ichikawa does not explicitly disclose wherein a thickness of the thermal oxide layer is less than a thickness of the first oxide layer.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process SO scaled.' 531 F.2d at 1053, 189 USPQ at 148.). In Gardner V. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the thickness of the first oxide layer and the thermal oxide layer to have the claimed thickness ratio in order to optimize gate reliability. (R. Siemieniec et al., "A SiC Trench MOSFET concept offering improved channel mobility and high reliability," 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), Warsaw, Poland, 2017, pp. P. 1-P.13)
Regarding claim 25, Onose as modified by Ichikawa discloses the method of claim 21, wherein a gate conductive layer and source conductive layer are formed.
Onose as modified by Ichikawa does not disclose wherein forming the gate conductive layer and the source conductive layer comprises depositing a metal layer on the SiC substrate; and reacting the metal layer with the top surface of the SiC mesa structure and the bottom of the trench exposed by the first oxide layer to form metal silicides.
However, Shimizu discloses depositing a metal (nickel, deposited by sputtering [0074])) on the SiC substrate in the bottom of the trench [0074]) and then reacting the metal layer (the nickel layer [0074]) with the top surface of the SiC mesa structure and the bottom of the trench exposed by the first oxide layer to form metal silicides (nickel silicide) by the process of annealing [0074].
Therefore, it would have been obvious to a person of ordinary skill in the art before the date of filing to form the gate and source electrodes by depositing a metal layer on the SiC substrate; and reacting the metal layer with the top surface of the SiC mesa structure and the bottom of the trench exposed by the first oxide layer to form metal silicides, in order to reduce the resistivity of these layers, thereby reducing the power dissipation and improving the switching efficiency of the device.
Regarding claim 26, Onose as modified by Ichikawa as in claim 21 discloses the method of claim 21, further comprising: forming an insulation layer (33) on the first oxide layer and the gate conductive layer.
Onose as modified by Ichikawa as in claim 21 does not teach:
forming a second oxide layer on the first oxide layer, the gate conductive layer, and the source conductive layer;
forming a nitride layer on the second oxide layer;
and forming an insulation layer on the nitride layer, wherein the insulation layer comprises borophosphosilicate glass.
However, Ichikawa teaches placing an insulating layer (comprising borophosphosilicate glass) on the source conductive layer, as well as on the first oxide layer and the gate conductive layer (figure 2, 13).
Furthermore, although Ichikawa, in the embodiment illustrated by figure 14, does not explicitly disclose:
forming a second oxide layer on the first oxide layer, the gate conductive layer, and the source conductive layer;
forming a nitride layer on the second oxide layer;
and forming an insulation layer on the nitride layer, wherein the insulation layer comprises borophosphosilicate glass,
Ichikawa suggests that the insulating layer 13 may comprise a stacked layer of films, including silicon dioxide, silicon nitride, and borophosphosilicate glass [0053].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to replace the borophosphosilicate glass layer 13 of Ichikawa, as illustrated in figure 14, with a layer comprising stacked layers of silicon dioxide (i.e.: a second oxide layer on the first oxide layer (11) and the conductive layer (14)), a silicon nitride dielectric layer on the silicon dioxide layer, and an insulating layer of borophosphosilicate glass, as disclosed by Ichikawa as an alternative, in order to increase the insulator layer lifetime. (L. A. Lipkin and J. W. Palmour, "Insulator investigation on SiC for improved reliability," in IEEE Transactions on Electron Devices, vol. 46, no. 3, pp. 525-532, March 1999).
Regarding claim 27, Onose as modified by Ichikawa discloses the method of claim 26, wherein a second oxide layer and a nitride layer are formed.
Onose, as modified by Ichikawa in claim 26, lacks the specific disclosure wherein a thickness of the second oxide layer is less than a thickness of the nitride layer.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process SO scaled.' 531 F.2d at 1053, 189 USPQ at 148.). In Gardner V. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the layers of Onose as modified by Ichikawa to have the claimed thickness ratio in order to increase the insulator layer lifetime (Lipkin et al.).
Regarding claim 28, Onose as modified by Ichikawa as in claim 26 discloses the method of claim 26, wherein the second oxide layer is in contact with the first oxide layer, the gate conductive layer, and the source conductive layer (Onose figure 11 shows that the second oxide layer, part of layer 33 in figure 11, is in contact with the first oxide layer (334), the gate conductive layer (23), and the source conductive layer (comprising the layers 221 and 22).
Claims 24, 29, 31, and 32 are rejected under 35 U.S.C. 103 as being unpatentable Onose et al. US 20050218424 in view of Ichikawa US 20240055258 and further in view of Seki JP 2008311406.
Regarding claim 24, Onose as modified by Ichikawa discloses the method of claim 21, wherein a gate conductive layer (figure 11, 23) and source conductive layer(figure 11, 221) are formed.
Onose as modified by Ichikawa does not disclose wherein the gate conductive layer and the source conductive layer are metal silicides: Onose is silent regarding the composition of the gate conductive layer (figure 11, 23) and the source conductive layer (figure 11, 221).
However, Shimizu discloses using a metal silicide (nickel silicide [0074]) to form the gate and source conductive layers.
Therefore, it would have been obvious to a person of ordinary skill in the art before the date of filing to form gate and source contact layers of metal silicide in order to reduce the resistivity of these layers, thereby reducing the power dissipation and improving the switching efficiency of the device (K. Shenai, P. A. Piacente, C. S. Korman and B. J. Baliga, "High- performance vertical-power DMOSFETs with selectively silicided gate and source regions," in IEEE Electron Device Letters, vol. 10, no. 4, pp. 153-155, April 1989).
Regarding claim 29, Onose discloses method for manufacturing a semiconductor device, comprising:
etching a trench (figure 11, 32 - [0030] explains that the trenches are formed by etching) in a SiC substrate to form a SiC mesa structure (see the mesas formed by the trenches 32 in figure 11) ;
forming a gate region (figure 11, 13) on a sidewall of the SiC mesa structure and a bottom of the trench (the formation of the gate region in the bottom and sidewalls of the mesa structure by ion implantation is described in [0018]);
wherein the oxide layer exposes the bottom of the trench (see figure 11, where the bottom of the trench 32 is not covered by the oxide layer 334);
Onose lacks after forming the gate region, performing a chemical vapor deposition process to form forming an oxide layer on the sidewall of the SiC mesa structure, and after the chemical vapor deposition process, performing a thermal oxidation treatment to oxidize the sidewall of the SiC mesa structure to form a thermal oxide layer between the first oxide layer and the SiC mesa structure.
However, Ichikawa discloses [0086] that his analogous silicon dioxide film 11 is deposited by a CVD process to line the sidewalls of similar trenches).
Therefore, it would have been obvious to a person of ordinary skill in the art before the time of filing to use the CVD process to form a first oxide layer, in order to precisely control the thickness and chemical purity of the first oxide layer.
Ononse as thus modified by Ichikawa lacks after the chemical vapor deposition process, performing thermal oxidation treatment to form a thermal oxide layer between the first oxide layer and the sidewalls of the first and second trench structures.
However, Seki discloses that silicon dioxide insulating film layer 38 [0029] lines the trench (figure D), and that a thermal oxidation process is performed on this layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to use the method of Seki to form a thermal oxide layer between the first oxide layer and the sidewalls of the first and second trench structures of Onose as modified by Ichikawa in order to improve electrical performance by creating a thermal oxide layer that has a smoother transition layer with more precisely controlled thickness.
Regarding claim 30, Onose as modified by Ichikawa and Seki discloses the method of claim 29, wherein the thermal oxide layer and the first oxide layer are formed (comprising layer 334 of figure 11).
Onose as modified by Ichikawa and Seki, as in claim 29, lacks specifically disclosing wherein the thermal oxide layer has a higher density than the first oxide layer does.
MPEP 2144.04 IV A states:
Changes in Size/Proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process SO scaled.' 531 F.2d at 1053, 189 USPQ at 148.). In Gardner V. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, because the choice is either the thermal oxide layer has a higher density than the first oxide layer, vice versa, or they are equal, to try each of the three choices to see which one works the best in combination and it would be obvious for the user to choose wherein the thermal oxide layer has a higher density than the first oxide layer, in order to improve gate reliability.
Regarding claim 31, Onose as modified by Ichikawa and Seki discloses the method of claim 29, further comprising:
forming a drain region (figure 11, 10) and a source region (figure 11, 10) in the SiC substrate [0002], wherein
the drain region (figure 11, 10) adjoins a bottom of the SiC substrate (see figure 11),
the source region is above the drain region (see figure 11, where source 12 is above drain 10), and
etching the trench (figure 11, 32 - [0030] explains that the trenches are formed by etching) in the SiC substrate is performed such that the SiC mesa structure (see the mesa formed by the trenches 32 in figure 11) has a portion of the source region (figure 11 shows that the mesa between trenches 32 comprises a portion of source region 12); and
forming a source conductive layer (221) on the portion of the source region in the SiC mesa structure (figure 11 shows that the mesa between trenches 32 comprises a portion of source region 12).
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Regarding claim 32, Onose as modified by Ichikawa and Seki discloses the method of claim 29, further comprising:
forming a gate extension region in the SiC substrate (see the gate extension region indicated by the arrow on figure 11, element 334),
wherein etching the trench in the SiC substrate is performed such that the SiC mesa structure has a portion of the gate extension region (see the gate extension region portion of element 334 in figure 11, indicated by an arrow and label - the trench is etched so that a portion of the gate extension region is in the SiC mesa) ,
wherein forming the gate region is performed such that the gate region is connected with the gate extension region (figure 11, element 334 comprises both the gate region and the gate extension region, which are in contact.)
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Onose as modified by Ichikawa and Seki and further in view of Bhalla et al. US 20160268446.
Regarding claim 33, Onose as modified by Ichikawa and Seki discloses the method of claim 32, further comprising: forming the gate extension region and forming the gate region (figure 11, 13), and then forming a channel implantation region (figure 12, implant 1201 is then applied to form vertical channel regions 602a and 602b ) in the SiC mesa structure.
Onose as modified by Ichikawa and Seki lacks wherein after forming the gate extension region, and prior to forming the gate region, forming a channel implantation region in the SiC mesa structure.
Bhalla discloses first forming a gate extension region (figure 11, top gate region 605 is created with a low energy implant 1101), doped channel region (in figure 4, channel region 230 is formed by implantation 204), then the gate region is formed [0019].
Therefore, it would have been obvious to a person of ordinary skill in the art before the time of filing to form these features in the order described by Bhalla in order to achieve improved threshold voltage control [0003].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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