DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10-16 and 24-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsiao et al. US 2014/0070422 A1.
Regarding claims 1 and 10-14, Hsiao discloses:
A stacked integrated circuit (IC) device (Fig. 3 in view of Fig. 2a) comprising:
a first die (32 para 0022) including active circuitry (31 memory dies) and a power distribution network (PDN) (35 vias), the first die having a first set of contacts (36 solder balls) on a first side (bottom) of the first die;
a second die (12) coupled, on a first side (top) of the second die, to the first side of the first die, wherein the second die includes, on a second side of the second die, a second set of contacts (47 as shown in Figs. 4e and 4f) to electrically connect circuitry of the second die to a substrate (11); and
an integrated capacitor device (ICD) (20 as shown in Fig. 2a) coupled to the first side of the first die (see Fig. 3), wherein the ICD (20) is electrically connected (through 13 as shown in Fig. 1a), via the first set of contacts (25 as shown in Fig. 2a), to the PDN and includes one or more through-ICD conductors (24 as shown in Fig. 2a) to electrically connect the PDN to the substrate (11 as shown in Fig. 1a).
(claim 10) a third set of contacts (Fig. 1a; 7, 9).
(claim 11) second die includes one or more through silicon vias (para 0032; through vias formed in the die 12).
(claim 12) a second side of the first die (top of bottom 31), a fourth set of contacts (para 0022; electrically coupled to each other through, for example, through vias, wire bonds, or the like) to electrically connect the stacked IC device to another device (another memory chip 31).
(claims 13 and 14) Fig. 3, paras 0021-0024; PoP device 30 inclusive of memory stack 32 and logic/IPD package 10.
Regarding claims 15, 16 and 24-27, Hsiao discloses:
A device comprising:
a stacked integrated circuit (IC) device (Fig. 3 in view of Fig. 2a), comprising:
a first die (32 para 0022) including active circuitry (31 memory dies) and a power distribution network (PDN) (35 vias), the first die having a first set of contacts (36 solder balls) on a first side (bottom) of the first die;
a second die (12) coupled, on a first side (top) of the second die, to the first side of the first die, wherein the second die includes, on a second side of the second die, a second set of contacts (47 as shown in Figs. 4e and 4f) to electrically connect circuitry of the second die to a substrate (11); and
an integrated capacitor device (ICD) (20 as shown in Fig. 2a) coupled to the first side of the first die (see Fig. 3), wherein the ICD (20) is electrically connected (through 13 as shown in Fig. 1a), via the first set of contacts (25 as shown in Fig. 2a), to the PDN and includes one or more through-ICD conductors (24 as shown in Fig. 2a) to electrically connect the PDN to the substrate (11 as shown in Fig. 1a).
(claim 16) at least one second device (additional 20 shown in Fig. 2a).
(claim 24) a third set of contacts (Fig. 1a; 7, 9).
(claim 25) a second side of the first die (top of bottom 31), a fourth set of contacts (para 0022; electrically coupled to each other through, for example, through vias, wire bonds, or the like) to electrically connect the stacked IC device to another device (another memory chip 31).
(claims 26 and 27) Fig. 3, paras 0021-0024; PoP device 30 inclusive of memory stack 32 and logic/IPD package 10.
Regarding claim 28, Hsiao discloses:
A method of fabricating a stacked integrated circuit (IC) device (Fig. 3 in view of Fig. 1a/2a), the method comprising:
coupling a first side (top) of a second die (12) to a first side of a first die (32 para 0022), wherein the first die includes a first set of contacts (36 solder balls) on the first side of the first die, active circuitry (31 memory dies), and a power distribution network (PDN) (35 vias), and wherein the second die includes, on a second side (bottom) of the second die, a second set of contacts (47 as shown in Figs. 4e and 4f) to electrically connect circuitry of the second die to a substrate (11); and
coupling, via the first set of contacts, an integrated capacitor device (ICD) (20 as shown in Fig. 2a) to the first side of the first die (see Fig. 3), wherein the ICD (20) includes one or more through-ICD conductors (24 as shown in Fig. 2a) to electrically connect the PDN to the substrate (11 as shown in Fig. 1a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5-9, 17, 21-23, 29 and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al. US 2014/0070422 A1.
Regarding claims 2, 5-9, 17, 21-23, 29 and 30, although Hsiao does not specifically disclose “(claims 2, 17 and 29) … wherein at least one edge of the first die overhangs at least one edge of the second die to define an overhang region, and wherein the ICD is disposed within the overhang region”; “(claims 5 and 21) … wherein at least two edges of the first die overhang at least two edges of the second die to define at least two overhang regions, and wherein the ICD is disposed within a first overhang region of the at least two overhang regions, and further comprising another integrated device disposed within a second overhang region of the at least two overhang regions”; “(claims 8 and 22) wherein the second die is disposed between the first overhang region and the second overhang region”; and “(claims 9, 23 and 30) wherein at least one edge of the second die extends past at least one edge of the first die to define at least one underhang region, and further comprising another integrated device (Fig. 1a and 3, another 20) disposed within the at least one underhang region”, Hsiao discloses connections regions ranging across the entire surface of first package 10 as shown in Fig. 1a while also noting in para 0022 that “the second package 32 may also incorporate other chips, dies, packages, or electronic circuitry depending on the intended use or performance needs of the PoP device 30”. As a result, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine a configuration in which the upper package structure 32 would comprise a larger length such that an overhang would occur having the discrete device 20 underneath (see Fig, 1a and 3) thereby increasing functionality of the overall PoP device 30.
(claim 6) a second ICD (Figs.1a and 3; 20).
(claim 7) a first and second set of conductors (25) (Fig. 2a in view of Figs. 1a and 3; 20 shown on left and right sides).
Claims 3, 4 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al. US 2014/0070422 A1 in view of Kim et al. US 2020/0273801 A1.
Regarding claims 3, 4 and 18-20, Hsiao does not disclose:
(claims 3 and 18) further comprising mold compound at least partially encapsulating the first die, the second die, and the ICD to form a packaged IC device; (claims 4 and 19) further comprising one or more conductors electrically connected to the first die and passing through the mold compound to provide an electrical connection between the first die and the substrate.
Kim discloses a publication from a similar field of endeavor in which:
(claims 3 and 18) further comprising mold compound (700) at least partially encapsulating the first die (400) and the second die (300) to form a packaged IC device (10); (claims 4 and 19) further comprising one or more conductors (500) electrically connected to the first die and passing through the mold compound to provide an electrical connection between the first die and the substrate (100) (refer to Fig. 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the molding compound and conductor electrically connecting the similar first die to the substrate of Kim within the similar PoP device of Hsiao including “the ICD” to further increase functionality allowing direct access to the first die from the substrate and vice versa.
(claim 20) Hsiao (Fig. 3 in view of Fig. 2a) - wherein the first die further includes input/output (I/O) circuitry (36), and the one or more conductors (9) are connected to the I/O circuitry to provide a data path between the first die (32) and another device (another 20) that is couple to the substrate (11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893
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