Prosecution Insights
Last updated: April 19, 2026
Application No. 18/454,444

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Aug 23, 2023
Examiner
LIU, BENJAMIN T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toshiba Electronic Devices & Storage Corporation
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
87%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
511 granted / 687 resolved
+6.4% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
48 currently pending
Career history
735
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 687 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 6-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected process and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/20/2026. Applicant’s election without traverse of claims 1-5 in the reply filed on 1/20/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sun et al. (US 2023/0036698) (“Sun”). With regard to claim 1, fig. 3 of Sun discloses a semiconductor device, comprising: a nitride semiconductor layer (5, 4) including a first layer 4, and a second layer 5 located on the first layer 4, the second layer 5 having a wider bandgap (AlGaN) than the first layer (GaN); a source electrode 10 located on the nitride semiconductor layer (5, 4), the source electrode 10 contacting the nitride semiconductor layer (5, 4); a drain electrode 9 located on the nitride semiconductor layer (5, 4), the drain electrode 9 being positioned distant to the source electrode 10 in a first direction (left to right, fig. 3), the drain electrode 9 contacting the nitride semiconductor layer (5, 4); a gate electrode 11 positioned between the source electrode 10 and the drain electrode 9, the gate electrode 11 not contacting (7 in between 11 and 5) the nitride semiconductor layer 9; an insulating film 6 located on the nitride semiconductor layer (5, 4) between the source electrode 10 and the drain electrode 9; and a conductor layer 8 positioned between the gate electrode 11 and the drain electrode 9, the conductor layer 8 contacting the nitride semiconductor layer (5, 4), the conductor layer 8 being electrically connected with the drain electrode 9, the drain electrode 9 including a first part (vertical portion of 9) contacting the nitride semiconductor layer (5, 4), and a second part (horizontal extending portion of 9) positioned further toward the conductor layer 8 side than the first part (vertical portion of 9) in the first direction (left to right in fig. 3), the insulating film 6 including a portion (portion of 6 between 8 and 9) positioned between the conductor layer 8 and the drain electrode 9, the second part (extending horizontal portion of 9) being located on the portion (portion of 6 between 8 and 9) of the insulating film 6. With regard to claim 3, fig. 3 of Sun discloses that the second part (extending horizontal portion of 9) of the drain electrode 9 contacts the conductor layer 8. With regard to claim 4, fig. 3 of Sn discloses a distance between the conductor layer 8 and the first part of the drain electrode 9 in the first direction (left to right) is less than a distance between the gate electrode 11 and the conductor layer 8 in the first direction (left to right). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (US 2023/0036698) (“Sun”) in view of Mirua et al. (US 9,306,051) (“Mirua”). With regard to claim 5, fig. 3 of Sun disclose that the insulating film 6 includes: a first film located at a surface of the nitride semiconductor layer (4, 5). Sun does not disclose a second film located on the first film, the second film is thicker than the first film, the gate electrode is located on the first film, and the second film covers the gate electrode. However, fig. 5 of Mirua discloses a second film IL1 located on the first film G1, the second film IL1 is thicker than the first film G1, the gate electrode GE is located on the first film G1, and the second film IL1 covers the gate electrode GE. Therefore, it would have been obvious to one of ordinary skill in the art to form the transistor of Sun with the interlayer insulating film as taught in Mirua in order to provide a protective film over the transistor. See col. 20 ll. 5-6 of Mirua. Allowable Subject Matter Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fig. 1 of Huang et al. (US 11201234) discloses an insulating film 116 between the conductor layer 142 and drain electrode 148. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 23, 2023
Application Filed
Mar 09, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604522
UNIVERSAL ELECTRICALLY INACTIVE DEVICES FOR INTEGRATED CIRCUIT PACKAGES
2y 5m to grant Granted Apr 14, 2026
Patent 12588116
MICROWAVE COOKING APPARATUS, CONTROL METHOD AND STORAGE MEDIUM
2y 5m to grant Granted Mar 24, 2026
Patent 12557677
BACKSIDE POWER DISTRIBUTION NETWORK SEMICONDUCTOR ARCHITECTURE USING DIRECT EPITAXIAL LAYER CONNECTION AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Feb 17, 2026
Patent 12550797
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Feb 10, 2026
Patent 12538581
INTEGRATED CIRCUIT INCLUDING CONNECTION LINE
2y 5m to grant Granted Jan 27, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
87%
With Interview (+12.6%)
3y 1m
Median Time to Grant
Low
PTA Risk
Based on 687 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month