DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
The applicant elected invention II without traverse on March 5, 2026, and has canceled the non-elected claims.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes: TRANSISTOR WITH A FERROELECTRIC DIELECTRIC LAYER
Paragraphs 26, 35, and 47 of the specification contain the word “supper lattice”, which is apparently a typographical error.
Claim Objections
Claims 25 and 27 recite “supper lattice”, which is apparently a typographical error.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The terms “first oxide film” and “second oxide film” in these claims are used in such a way that they could be interpreted to refer to single respective layers, or alternatively to refer to any of the first and second types of layers in the disclosed alternating stack. For example, claim 8 recites “performing one or more first cycles to form a first oxide film; and performing one or more second cycles to form a second oxide film”, which would seem to refer to two discrete layers. However, claim 11 recites “forming a dielectric layer over the ferroelectric layer” and claim 12 recites that “the dielectric layer is in contact with the first oxide film.” This would only be true for single recited first oxide film if there is only one such film in the ferroelectric layer, which does not seem to accord with the specification. As set forth in In re Miyazaki, “if a claim is amenable to two or more plausible claim constructions, the USPTO is justified in requiring the applicant to more precisely define the metes and bounds of the claimed invention by holding the claim unpatentable under 35 U.S.C. §112, second paragraph, as indefinite.” 89 USPQ2d 1207, 1211 (Bd. Pat. App. & Int. 2008). For present purposes, the examiner will assume the latter interpretation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 7-9, 11-13, 15-17, and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Jo, US 2024/0213349 A1, in view of Majhi, US 2022/0199801 A1.
Claim 7: Jo discloses
forming an underlayer (11) over a support substrate, wherein the underlayer is a single crystal layer;
“The channel 11 may be formed as a substrate base, and/or may be implemented as a separate material layer.” [0066]
performing an atomic layer deposition process to form a ferroelectric layer (30) over the underlayer, wherein the ferroelectric layer has an orthorhombic phase ([0083]);
“the ferroelectric layer 30 may have a ZrO2/HZO thin film structure” [0082]. “In an electronic device and an electronic apparatus using the same according to various embodiments, thin film deposition may be performed by using any of various deposition methods such as atomic layer deposition (ALD)” [0131].
and forming an electrode layer (50) over the ferroelectric layer (FIG. 1).
PNG
media_image1.png
391
472
media_image1.png
Greyscale
Jo does not disclose what the channel layer 11 is formed over when it is implemented as a material layer separate from the substrate. Majhi discloses a transistor with a ferroelectric oxide layer. The transistor has a channel layer 415 grown epitaxially above a substrate ([0028]). It would have been obvious to form the channel layer of Jo by epitaxy as a well-known method of forming a channel layer.
Claim 8: the atomic layer deposition process comprises: performing one or more first cycles to form a first oxide film; and performing one or more second cycles to form a second oxide film, wherein the first oxide film has a composition different from a composition of the second oxide film. “[t]he ferroelectric layer 30 has a Z/HZO structure including the first oxide layer 31 formed of ZrO2, and the second oxide layer 35 formed using a solid solution deposition method of alternately depositing the HfO2 layer 35a and the ZrO2 layer 35b.” [0093]. As these are deposited by ALD ([0131]), they will necessarily each be deposited by one or more cycles, as ALD is performed in cycles.
Claim 9: the first oxide film is hafnium oxide ([0093], FIG. 4B).
Claim 11: Jo discloses forming a dielectric layer (the top layer of ZrO2 in 30, FIG. 1) over the ferroelectric layer, wherein the dielectric layer is Al203, HfO2, ZrO2, TiO2, Ta20s, Y203, SiO2, SiCN, or Si3N4.
Claim 12: the dielectric layer is in contact with the first oxide film.
Claim 13: the second oxide film is zirconium oxide ([0093]).
Claim 15: forming a dielectric layer (the top layer of HfO2 in 30) over the ferroelectric layer, wherein the dielectric layer is A12O3, HfO2, ZrO2, TiO2, Ta20s, Y203, SiO2, SiCN, or Si3N4.
Claim 16: the dielectric layer is in contact with the second oxide film.
Clam 17: the second oxide film is made of one or more oxide materials including Zr, Si, Sr, Y, La, Ge, Al, or a combination thereof (ZrO2, [0093]).
Claim 21: Jo in view of Majhi discloses
epitaxial growing an underlayer (11 of Jo) over a semiconductor substrate, wherein the underlayer is a single crystal layer;
The transistor of Majhi has a channel layer 415 grown epitaxially above a substrate ([0028]). It would have been obvious to form the channel layer of Jo by epitaxy as a well-known method of forming a channel layer. Epitaxy produces single crystal layers.
performing an atomic layer deposition process to form a ferroelectric layer over the underlayer, wherein the ferroelectric layer has an orthorhombic phase (Jo [0083]);
“the ferroelectric layer 30 may have a ZrO2/HZO thin film structure” Jo [0082].
“In an electronic device and an electronic apparatus using the same according to various embodiments, thin film deposition may be performed by using any of various deposition methods such as atomic layer deposition (ALD)” Jo [0131].
and forming an electrode layer (50 of Jo) over the ferroelectric layer.
Claim 22: the underlayer is a semiconductor layer (Jo [0066]).
Claim 23: Jo discloses that “the channel 11 May be formed by injecting impurities into different regions of a semiconductor substrate” [0067]. Those in the art would have recognized that when the separate layer implementation of channel layer 11 is a semiconductor layer ([0066]), that this could also be doped. It was well-known in the art to dope semiconductors to increase their conductivity, as Jo discloses ([0064]).
Claim 24: the underlayer is silicon, germanium or silicon germanium (Jo [0066]).
Claim 25: the ferroelectric layer comprises a supper lattice structure (orthorhombic crystal of alternating layers of HfO2/ZrO2 - Jo [0093]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Prasad, US 2020/0203380 A1. Claims 8-18 are rejected under 35 U.S.C. 103 as being unpatentable over Prasad in view of Jo.
Claim 7: Prasad discloses
forming an underlayer (40) over a support substrate (10);
forming a ferroelectric layer (21) over the underlayer,
and forming an electrode layer (51) over the ferroelectric layer (FIG. 7).
PNG
media_image2.png
432
664
media_image2.png
Greyscale
Prasad does not disclose many of the details of the embodiment of FIG. 7. However, details are disclosed for other embodiments that read on claim 7.
Prada disclose that “The semiconductor substrate may be a bulk semiconductor substrate in which the semiconductor material layer 710 extends from a front surface to a backside surface, or may be a semiconductor-on-insulator (SOI) substrate including a buried insulator layer (not shown) underlying the semiconductor material layer 710 and a handle substrate (not shown) that underlies the buried insulating layer. For example, the semiconductor substrate may comprise a commercially available single crystalline bulk silicon wafer or a commercially available semiconductor-on-insulator substrate.” [0100]. Thus channel layer 710 is single crystal. It would have been expected or obvious for the channel layer 40 of FIG. 7 to also be single crystal.
Prasad discloses that “the ferroelectric gate dielectric layer 750L can be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.” [0105]. It would have been expected or obvious for the ferroelectric layer 21 of FIG. 7 to be formed by ALD.
Prasad discloses that “The ferroelectric gate dielectric layer 750L includes, and/or consists essentially of, at least one ferroelectric material such as hafnium oxide (such as hafnium oxide containing at least one dopant selected from Al, Zr, and Si and having a ferroelectric non-centrosymmetric orthorhombic phase)”. It would have been obvious to have used the same material for the ferroelectric layer 21 of FIG. 7.
Claim 8: Prasad discloses a ferroelectric gate dielectric layer. Jo discloses that “[t]he ferroelectric layer 30 has a Z/HZO structure including the first oxide layer 31 formed of ZrO2, and the second oxide layer 35 formed using a solid solution deposition method of alternately depositing the HfO2 layer 35a and the ZrO2 layer 35b.” [0093]. It would have been obvious to have used such a structure in Prasad as a known effective ferroelectric layer for transistors. In Prasad in view of Jo, performing the atomic layer deposition process comprises: performing one or more first cycles to form a first oxide film; and performing one or more second cycles to form a second oxide film, wherein the first oxide film has a composition different from a composition of the second oxide film. As the layers of Jo are deposited by ALD ([0131]), they will necessarily each be deposited by one or more cycles, as ALD is performed in cycles.
Claim 9: the first oxide film is hafnium oxide (Jo [0093], FIG. 4B).
Claim 10: Prasad FIG. 7 shows the ferroelectric layer 21 in contact with the underlayer 40, and thus the bottom of the ferroelectric layer (the first oxide film) will be in contact with the underlayer.
Claim 11: Jo discloses forming a dielectric layer (the second layer of ZrO2 in the superlattice of Jo) over the ferroelectric layer, wherein the dielectric layer is Al203,HfO2, ZrO2, TiO2, Ta20s, Y203, SiO2, SiCN, or Si3N4.
Claim 12: the dielectric layer is in contact with the first oxide film.
Claim 13: the second oxide film is zirconium oxide ([0093]).
Claim 14: the second oxide film is in contact with the underlayer. This will be true in a case in which the ZrO2 is deposited first.
15. (Original) The method of claim 14, further comprising: forming a dielectric layer (a top HfO2 layer) over the ferroelectric layer, wherein the dielectric layer is Al2O3, HfO2, ZrO2, TiO2, Ta20s, Y203, SiO2, SiCN, or Si3N4.
Claim 16: the dielectric layer is in contact with the second oxide film.
Claim 17: the second oxide film (ZrO2) is made of one or more oxide materials including Zr, Si, Sr, Y, La, Ge, Al, or a combination thereof.
Claim 18: the second oxide film is in contact with the underlayer. This will be true in a case in which the ZrO2 is deposited first.
Claims 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Prasad in view of Jo and Weon, US 2003/0104645 A1.
Claim 26: Jo discloses that the channel layer 11 can be various semiconductor materials, including SiGe [0066]. It would have been obvious to use this in Prasad as a known channel material for ferroelectric transistors. Prasad discloses that substrate 10 can be “The substrate 10 may comprise any suitable supporting substrate, such as a semiconductor wafer” [0072], of which by far the most common type is a silicon wafer (Prasad [0100]). Weon teaches that to grow a SiGe layer on a silicon substrate, it is desirable to first etch the oxide off the substrate ([0025]). Thus those in the art would see that in having a SiGe channel layer in Jo, it would be desirable to:
etching a semiconductor substrate to remove an oxide;
forming an underlayer over the semiconductor substrate,
The underlayer (channel layer) is a single crystal layer, as epitaxy forms single crystal layers.
Prasad discloses that “the ferroelectric gate dielectric layer 750L can be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.” [0105]. It would have been expected or obvious for the ferroelectric layer 21 of FIG. 7 to be formed by ALD.
Prasad discloses that “The ferroelectric gate dielectric layer 750L includes, and/or consists essentially of, at least one ferroelectric material such as hafnium oxide (such as hafnium oxide containing at least one dopant selected from Al, Zr, and Si and having a ferroelectric non-centrosymmetric orthorhombic phase)”. It would have been obvious to have used the same material for the ferroelectric layer 21 of FIG. 7.
Prasad discloses forming an electrode layer ([0050]) over the oxide-based ferroelectric layer.
Claim 27: Prasad discloses a ferroelectric gate dielectric layer. Jo discloses that “[t]he ferroelectric layer 30 has a Z/HZO structure including the first oxide layer 31 formed of ZrO2, and the second oxide layer 35 formed using a solid solution deposition method of alternately depositing the HfO2 layer 35a and the ZrO2 layer 35b.” [0093]. It would have been obvious to have used such a structure in Prasad as a known effective ferroelectric layer for transistors. This is
an HfO2-ZrO2 supper lattice structure.
Claim 28: the oxide-based ferroelectric layer (21) is in physical contact with the underlayer (40) (Prasad FIG. 7).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Warusawithana et al, “A Ferroelectric Oxide Made Directly on Silicon”, SCIENCE, VOL 324 p. 367 (2009).
Nukala et al, Direct Epitaxial Growth of Polar (1 − x)HfO2−(x)ZrO2 Ultrathin Films on Silicon”, ACS Appl. Electron. Mater. 2019, 1, 2585−2593.
Cheema et al, “Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors”, Nature, Vol 604, p. 64, (2022).
Li et al, “Enhancing ferroelectric stability: wide-range of adaptive control in epitaxial HfO2/ZrO2 superlattices”, Nature Communications 16:6417 (2025).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER BRADFORD/Primary Examiner, Art Unit 2897