DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The amended title overcomes the objection.
The previous indefiniteness rejection is overcome; see the new rejection below.
The applicant has changed the term “supper lattice” to “supperlattice”. This appears to still be a typographical error. The examiner’s examination of this application is based on the understanding that this is a typo for “superlattice”. If a supperlattice refers to something else, it is not clear from the disclosure what that might be.
The applicant states on page 12 that “[s]olely for the sake of argument, a person having ordinary skill in the art would not modify Jo's deposition method to include a greater number of alleged first oxide films 35a than the alleged second oxide films 35b because it would fundamentally destroy Jo's principle of operation.” The applicant states on page 13 that “[s]olely for the sake of argument, a plasma treatment of Jo [0131] refers to a treatment in addition to the deposition process, not within the deposition process, and thus does not teach the claimed second cycles include igniting a plasma from an oxidant as claimed.” The examiner understands the modifier “solely for the sake of argument” to mean that the applicant is not making a definite assertion on which the Office should rely about the prior art, but is rather making only a hypothetical argument based on a hypothetical premise. The examiner therefore does not take these arguments into account in considering the applicant’s July 14, 2026 response.
See the new art rejections below.
Specification
Paragraphs 26, 35, and 47 of the specification contain the word “supperlattice”, which is apparently a typographical error.
Claim Objections
Claims 25 and 27 recite “supperlattice”, which is apparently a typographical error.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-17 and 26-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 26 recite that “performing the atomic layer deposition process comprises forming alternately stacked first oxide films and second oxide films, a number of the first oxide films is greater than a number of the second oxide films”. This could be interpreted in two ways: that the total number of first oxide films is greater than the total number of second oxide films, or that the number of first oxide films per cycle is greater than the number of second oxide films per cycle. As set forth in In re Miyazaki, “if a claim is amenable to two or more plausible claim constructions, the USPTO is justified in requiring the applicant to more precisely define the metes and bounds of the claimed invention by holding the claim unpatentable under 35 U.S.C. §112, second paragraph, as indefinite.” 89 USPQ2d 1207, 1211 (Bd. Pat. App. & Int. 2008). For present purposes the examiner will use either interpretation.
The remaining claims are rejected based on their dependencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9, 11-13, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jo, US 2024/0213349 A1, in view of Majhi, US 2022/0199801 A1, or alternatively under 35 U.S.C. 103 as being unpatentable over Jo, Majhi, and Yoo, US 2018/0240804 A1.
Claim 7: Jo discloses
forming an underlayer (11) over a support substrate, wherein the underlayer is a single crystal layer;
“The channel 11 may be formed as a substrate base, and/or may be implemented as a separate material layer.” [0066]
performing an atomic layer deposition process to form a ferroelectric layer (30) over the underlayer, wherein the ferroelectric layer has an orthorhombic phase ([0083]);
“the ferroelectric layer 30 may have a ZrO2/HZO thin film structure” [0082]. “In an electronic device and an electronic apparatus using the same according to various embodiments, thin film deposition may be performed by using any of various deposition methods such as atomic layer deposition (ALD)” [0131].
and forming an electrode layer (50) over the ferroelectric layer (FIG. 1).
PNG
media_image1.png
391
472
media_image1.png
Greyscale
Jo does not disclose what the channel layer 11 is formed over when it is implemented as a material layer separate from the substrate. Majhi discloses a transistor with a ferroelectric oxide layer. The transistor has a channel layer 415 grown epitaxially above a substrate ([0028]). It would have been obvious to form the channel layer of Jo by epitaxy as a well-known method of forming a channel layer.
Claim 7 also recites that performing the atomic layer deposition process comprises forming alternately stacked first oxide films and second oxide films, a number of the first oxide films is greater than a number of the second oxide films. Jo discloses alternately stacked first oxide films and second oxide films (alternating stack 35, FIG. 1). Jo does not explicitly disclose that a number of the first oxide films is greater than a number of the second oxide films. As noted above in the 112 rejection, this has two potential meanings. Under either meaning, this feature is disclosed in the prior art.
Under the first meaning, that that the total number of first oxide films is greater than the total number of second oxide films, See Yoo, which discloses that the top and bottom layers of the stack are the same (135, [0045]-[0047]). Thus it was known to have one more of the first oxide film than the second oxide film.
Under the second meaning, that the number of first oxide films between adjacent second oxide films is greater than the number of second oxide films between adjacent first oxide films, this is a product-by-process claim, meaning that only the resulting structure is required. Two layers of the same material stacked one right on the other is the same as a single layer of the same thickness.
Claim 8: the first oxide films have a composition different from a composition of the second oxide film. “[t]he ferroelectric layer 30 has a Z/HZO structure including the first oxide layer 31 formed of ZrO2, and the second oxide layer 35 formed using a solid solution deposition method of alternately depositing the HfO2 layer 35a and the ZrO2 layer 35b.” [0093]. As these are deposited by ALD ([0131]), they will necessarily each be deposited by one or more cycles, as ALD is performed in cycles.
Claim 9: the first oxide films include hafnium oxide ([0093], FIG. 4B).
Claim 11: Jo discloses forming a dielectric layer (the top layer of ZrO2 in 30, FIG. 1) over the ferroelectric layer, wherein the dielectric layer is Al203, HfO2, ZrO2, TiO2, Ta20s, Y203, SiO2, SiCN, or Si3N4.
Claim 12: the dielectric layer is in contact with one of the first oxide films.
Claim 13: the second oxide films include zirconium oxide ([0093]).
Claim 15: forming a dielectric layer (the top layer of HfO2 in 30) over the ferroelectric layer, wherein the dielectric layer is A12O3, HfO2, ZrO2, TiO2, Ta20s, Y203, SiO2, SiCN, or Si3N4.
Claim 16: the dielectric layer is in contact with one of the second oxide films.
Clam 17: the second oxide films are made of one or more oxide materials including Zr, Si, Sr, Y, La, Ge, Al, or a combination thereof (ZrO2, [0093]).
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Jo, US 2024/0213349 A1, in view of Majhi, Popvici, 2023/0200078 A1, and Nakamura, US 2012/0094505 A1.
Claim 21: Jo in view of Majhi discloses
epitaxial growing an underlayer (11 of Jo) over a semiconductor substrate, wherein the underlayer is a single crystal layer;
The transistor of Majhi has a channel layer 415 grown epitaxially above a substrate ([0028]). It would have been obvious to form the channel layer of Jo by epitaxy as a well-known method of forming a channel layer. Epitaxy produces single crystal layers.
performing an atomic layer deposition process to form a ferroelectric layer over the underlayer, wherein the ferroelectric layer has an orthorhombic phase (Jo [0083]);
“the ferroelectric layer 30 may have a ZrO2/HZO thin film structure” Jo [0082].
“In an electronic device and an electronic apparatus using the same according to various embodiments, thin film deposition may be performed by using any of various deposition methods such as atomic layer deposition (ALD)” Jo [0131].
and forming an electrode layer (50 of Jo) over the ferroelectric layer.
Claim 21 also recites that performing the atomic layer deposition process comprises: performing first cycles to form first oxide layers (Jo [0058]-[0059]); and performing second cycles to form second oxide layers (Jo [0058]-[0059]), wherein the second cycles include igniting a plasma from an oxidant. Jo does not disclose the igniting a plasma, but it was known in the art. See Popovici, [0080]: “HZO is deposited S130 on the metal for forming a ferroelectric layer.… The precursors used may be HfCl4, ZrCl4, and H2O or any metalorganic compound with Hf and Zr such as cyclopentadienyl, amidinates, etc. in combination with H2O, ozone (O3), or oxygen plasma.” (Note that oxygen is an oxidant.) It was well-known that plasmas were commonly formed by ignition: “igniting the plasma of a treatment gas including the oxygen containing gas” (Nakamura [0012]). It would have been obvious to have formed the HZO second oxide layers by igniting an oxygen gas as known in the art to form such a layer.
Claim 22: the underlayer is a semiconductor layer (Jo [0066]).
Claim 23: Jo discloses that “the channel 11 May be formed by injecting impurities into different regions of a semiconductor substrate” [0067]. Those in the art would have recognized that when the separate layer implementation of channel layer 11 is a semiconductor layer ([0066]), that this could also be doped. It was well-known in the art to dope semiconductors to increase their conductivity, as Jo discloses ([0064]).
Claim 24: the underlayer is silicon, germanium or silicon germanium (Jo [0066]).
Claim 25: the ferroelectric layer comprises a supperlattice structure (orthorhombic crystal of alternating layers of HfO2/ZrO2 - Jo [0093]).
Claims 7-18 are rejected under 35 U.S.C. 103 as being unpatentable over Prasad, US 2020/0203380 A1 in view of Jo, or alternatively under 35 U.S.C. 103 as being unpatentable over Prasad, Jo, and Yoo, US 2018/0240804 A1.
Claim 7: Prasad discloses
forming an underlayer (40) over a support substrate (10);
forming a ferroelectric layer (21) over the underlayer,
and forming an electrode layer (51) over the ferroelectric layer (FIG. 7).
PNG
media_image2.png
432
664
media_image2.png
Greyscale
Prasad does not disclose many of the details of the embodiment of FIG. 7. However, details are disclosed for other embodiments that read on claim 7.
Prasad discloses that “[t]he semiconductor substrate may be a bulk semiconductor substrate in which the semiconductor material layer 710 extends from a front surface to a backside surface, or may be a semiconductor-on-insulator (SOI) substrate including a buried insulator layer (not shown) underlying the semiconductor material layer 710 and a handle substrate (not shown) that underlies the buried insulating layer. For example, the semiconductor substrate may comprise a commercially available single crystalline bulk silicon wafer or a commercially available semiconductor-on-insulator substrate.” [0100]. Thus channel layer 710 is single crystal. It would have been expected or obvious for the channel layer 40 of FIG. 7 to also be single crystal.
Prasad discloses that “the ferroelectric gate dielectric layer 750L can be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.” [0105]. It would have been expected or obvious for the ferroelectric layer 21 of FIG. 7 to be formed by ALD.
Prasad discloses that “The ferroelectric gate dielectric layer 750L includes, and/or consists essentially of, at least one ferroelectric material such as hafnium oxide (such as hafnium oxide containing at least one dopant selected from Al, Zr, and Si and having a ferroelectric non-centrosymmetric orthorhombic phase)”. It would have been obvious to have used the same material for the ferroelectric layer 21 of FIG. 7.
Claim 7 also recites that performing the atomic layer deposition process comprises forming alternately stacked first oxide films and second oxide films, a number of the first oxide films is greater than a number of the second oxide films. Jo discloses alternately stacked first oxide films and second oxide films (alternating stack 35, FIG. 1). It would have been obvious to have used such a structure in Prasad as a known effective ferroelectric layer for transistors. Jo does not explicitly disclose that a number of the first oxide films is greater than a number of the second oxide films. As noted above in the 112 rejection, this has two potential meanings. Under either meaning, this feature is disclosed in the prior art.
Under the first meaning, that that the total number of first oxide films is greater than the total number of second oxide films, See Yoo, which discloses that the top and bottom layers of the stack are the same (135, [0045]-[0047]). Thus it was known to have one more of the first oxide film than the second oxide film.
Under the second meaning, that the number of first oxide films between adjacent second oxide films is greater than the number of second oxide films between adjacent first oxide films, this is a product-by-process claim, meaning that only the resulting structure is required. Two layers of the same material stacked one right on the other is the same as a single layer of the same thickness.
Claim 8: Prasad discloses a ferroelectric gate dielectric layer. Jo discloses that “[t]he ferroelectric layer 30 has a Z/HZO structure including the first oxide layer 31 formed of ZrO2, and the second oxide layer 35 formed using a solid solution deposition method of alternately depositing the HfO2 layer 35a and the ZrO2 layer 35b.” [0093]. It would have been obvious to have used such a structure in Prasad as a known effective ferroelectric layer for transistors. In Prasad in view of Jo, performing the atomic layer deposition process comprises: performing one or more first cycles to form a first oxide film; and performing one or more second cycles to form a second oxide film, wherein the first oxide film has a composition different from a composition of the second oxide film. As the layers of Jo are deposited by ALD ([0131]), they will necessarily each be deposited by one or more cycles, as ALD is performed in cycles.
Claim 9: the first oxide films include hafnium oxide (Jo [0093], FIG. 4B).
Claim 10: Prasad FIG. 7 shows the ferroelectric layer 21 in contact with the underlayer 40, and thus the bottom of the ferroelectric layer (the first oxide films) will be in contact with the underlayer.
Claim 11: Jo discloses forming a dielectric layer (the second layer of ZrO2 in the superlattice of Jo) over the ferroelectric layer, wherein the dielectric layer is Al203,HfO2, ZrO2, TiO2, Ta20s, Y203, SiO2, SiCN, or Si3N4.
Claim 12: the dielectric layer is in contact with one of the first oxide films.
Claim 13: the second oxide films include zirconium oxide ([0093]).
Claim 14: one of the second oxide films is in contact with the underlayer. This will be true in a case in which the ZrO2 is deposited first.
15. (Original) The method of claim 14, further comprising: forming a dielectric layer (a top HfO2 layer) over the ferroelectric layer, wherein the dielectric layer is Al2O3, HfO2, ZrO2, TiO2, Ta20s, Y203, SiO2, SiCN, or Si3N4.
Claim 16: the dielectric layer is in contact with one of the second oxide films.
Claim 17: the second oxide films (ZrO2) are made of one or more oxide materials including Zr, Si, Sr, Y, La, Ge, Al, or a combination thereof.
Claim 18: one of the second oxide films is in contact with the underlayer. This will be true in a case in which the ZrO2 is deposited first.
Claims 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Prasad in view of Jo and Weon, US 2003/0104645 A1, or alternatively under 35 U.S.C. 103 as being unpatentable over Prasad in view of Jo, Weon, and Yoo.
Claim 26: Jo discloses that the channel layer 11 can be various semiconductor materials, including SiGe [0066]. It would have been obvious to use this in Prasad as a known channel material for ferroelectric transistors. Prasad discloses that substrate 10 can be “The substrate 10 may comprise any suitable supporting substrate, such as a semiconductor wafer” [0072], of which by far the most common type is a silicon wafer (Prasad [0100]). Weon teaches that to grow a SiGe layer on a silicon substrate, it is desirable to first etch the oxide off the substrate ([0025]). Thus those in the art would see that in having a SiGe channel layer in Jo, it would be desirable to:
etching a semiconductor substrate to remove an oxide;
forming an underlayer over the semiconductor substrate,
The underlayer (channel layer) is a single crystal layer, as epitaxy forms single crystal layers.
Prasad discloses that “the ferroelectric gate dielectric layer 750L can be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.” [0105]. It would have been expected or obvious for the ferroelectric layer 21 of FIG. 7 to be formed by ALD.
Prasad discloses that “The ferroelectric gate dielectric layer 750L includes, and/or consists essentially of, at least one ferroelectric material such as hafnium oxide (such as hafnium oxide containing at least one dopant selected from Al, Zr, and Si and having a ferroelectric non-centrosymmetric orthorhombic phase)”. It would have been obvious to have used the same material for the ferroelectric layer 21 of FIG. 7.
Prasad discloses forming an electrode layer ([0050]) over the oxide-based ferroelectric layer.
Claim 26 also recites that performing the atomic layer deposition process comprises forming alternately stacked first oxide films and second oxide films, a number of the first oxide films is greater than a number of the second oxide films. Jo discloses alternately stacked first oxide films and second oxide films (alternating stack 35, FIG. 1). Jo does not explicitly disclose that a number of the first oxide films is greater than a number of the second oxide films. As noted above in the 112 rejection, this has two potential meanings. Under either meaning, this feature is disclosed in the prior art.
Under the first meaning, that that the total number of first oxide films is greater than the total number of second oxide films, See Yoo, which discloses that the top and bottom layers of the stack are the same (135, [0045]-[0047]). Thus it was known to have one more of the first oxide film than the second oxide film.
Claim 27: Prasad discloses a ferroelectric gate dielectric layer. Jo discloses that “[t]he ferroelectric layer 30 has a Z/HZO structure including the first oxide layer 31 formed of ZrO2, and the second oxide layer 35 formed using a solid solution deposition method of alternately depositing the HfO2 layer 35a and the ZrO2 layer 35b.” [0093]. It would have been obvious to have used such a structure in Prasad as a known effective ferroelectric layer for transistors. This is
an HfO2-ZrO2 supperlattice structure.
Claim 28: the oxide-based ferroelectric layer (21) is in physical contact with the underlayer (40) (Prasad FIG. 7).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER BRADFORD/Primary Examiner, Art Unit 2897
Prosecution Insights