DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the REPUBLIC OF KOREA on 03/20/2023.
Election/Restrictions
Applicant's election without traverse of “Species A (Claims 1-12 and 18-25)” in the reply filed on December 5, 2025, is acknowledged. Claims 13-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8 and 10-12 are rejected under 35 U.S.C. 103 as being obvious over US 2024/0105622 A1; Said et al.; 03/2024; (“622”).
Regarding Claim 1. 622 teaches in Figs. 51B,53A and 54D about a memory device comprising:
a source line (Fig. 51B, grouped layer items 112,114, and 116, “the source-level material layers
110 include a source layer (112, 114, 116)”, [0291], Ln. 8-9);
a dummy stack structure (Fig. 51B, embodied by “the source-level insulating layer 117, and the optional source-select-level conductive layer 118”, [0206], Ln. 6-7) located on the source line (Fig. 51B, layer items 117 and 118 are located on the source line);
a main stack structure (Fig. 53A, “alternating stacks … of insulating layers (132 …) and
electrically conductive layers (146 …)”, [0294], Ln. 4-6) located on the dummy stack structure (Fig. 53A, main stack located on the dummy stack structure); and
a source contact (Fig. 54D, item 76) in contact with the source line while penetrating the main stack structure and the dummy stack structure (Fig. 54D, item 76 in contact with source line sub-layer item 114 while penetrating the main stack and the dummy stack),
wherein the dummy stack structure includes:
a first material layer (Fig. 54D, layer item 117) located on the source line; and
second material layers (Fig. 54D, layer item 118), and blocking insulating layers (Fig. 54D, item 124), located on the first material layer (Fig. 54D, items 118 and 124 are located on layer item 117), and
wherein the main stack structure includes insulating layers (Fig. 53A, “insulating layers … 132”, [0219], Ln. 18-19) and gate conductive layers (Fig. 53A, “control gate electrodes within each electrically conductive layer … 146”, [0218], Ln. 7-8), which are alternately stacked on the dummy stack structure.
622 does not teach about a memory device comprising:
wherein the dummy stack structure includes:
dummy conductive layers, located on the first material layer.
It would have been obvious to try by one of ordinary skill in the art, at the time the invention was made, to consider rearranging each of the blocking insulating layers farther away from the source contact along a horizontal direction while remaining within the second material layer; therefore, creating a dummy conductive layer that does not contact other conductive elements, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding Claim 6. 622 teaches in Figs. 54A and 54B about a memory device, wherein
the source contact penetrates the dummy stack structure between the dummy conductive layers to space apart the dummy conductive layers from each other (in Fig. 54A source contact item 76 penetrates vertically the level material layer item 110 (dummy stack is within the top region of item 110) and spaces apart the dummy conductive layers within memory blocks of area 100; indeed, this is better viewed in Fig. 54B which is a plane view of the layer stacks).
Regarding Claim 7. 622 teaches in Fig. 54D about a memory device, wherein
the first material layer (“layer 117 includes … silicon oxide”, [0145, Ln. 1-2]), the blocking insulating layers (“semiconductor oxide rails 124”, [209], Ln. 3), and the insulating layers (“insulating layers 132 include … silicon oxide”, [0153], Ln. 7-8) comprises an oxide layer.
Regarding Claim 8. 622 teaches in Fig. 54D about a memory device, wherein
the second material layers comprises a conductive layer (“conductive layer 118”, [0145], Ln. 6).
622 teaches does not teach about a memory device, wherein
the second material layers comprises a nitride layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to try using a nitride material because nitrides could have conductive properties depending on their structure and bonding, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Regarding Claim 10. 622 teaches in Fig. 54A about a memory device, wherein
a support structure (items 20) spaced apart from the source contact (items 20 are spaced apart from item 76), the support structure being in contact with the source line while penetrating the main stack structure and the dummy stack structure (items 20 are in contact with source line item 110 and penetrate main stack items 146 and 132).
Regarding Claim 11. 622 teaches in Fig. 54A about a memory device, wherein
the support structure penetrates at least one second material layer among the second material layers of the dummy stack structure and the first material layer (items 20 penetrate as deep as item 76 into item 110; therefore, items 20 at least penetrate a one second material layer).
Regarding Claim 12. 622 teaches in Fig. 10A about a memory device, wherein the support structure comprises an electrically inactive structure ([0197], Ln. 10).
622 teaches does not teach about a memory device, wherein the support structure comprises an oxide layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to try using an oxide material because oxide materials are well known in the art as insulators, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being obvious over US 2024/0105622 A1; Said et al.; 03/2024; (“622”) in view of US 2022/0336421 A1; Kim et al.; 10/2022; (“421”).
Regarding Claim 2. 622 teaches in Fig. 51B about a memory device, wherein
the source line includes first (layer item 112), second (layer item 116), and third source layers (layer item 114).
622 does not teach about a memory device, wherein
the source line includes a source pad.
421 teaches in Fig. 5C about a memory device, wherein
the source line (item 110) includes a source pad (item 181b).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the source pad of 421 to electrically connect the source contact to the source line in 622 to achieve a preferred “side profile of the first plug portion 181b may be determined depending on the extent of removing a semiconductor material layer of the source connection pattern 110 through a contact hole of the source contact plug 180” as taught by 421 in [0071], Ln. 6-10.
Regarding Claim 5. 421 teaches in Fig. 5C about a memory device, wherein
the source contact is in contact with the source pad (item 182 is in contact with item 181b; indeed, these two items are sub-parts of item 180).
Allowable Subject Matter
Claims 18-25 are allowed.
The following is an examiner’s statement of reasons for allowance:
After completing a thorough search of independent claim 18, the prior art of record taken either
singularly or in combination fails to anticipate or fairly suggest the limitations of the independent claim listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
Regarding independent claim 18, the prior art of record, alone or in combination does not disclose, teach or fairly suggest a method of manufacturing a memory device comprising:
forming a first and second isolation trenches spaced apart from each other in the second material layer on the etch stop layer; forming first and second blocking insulating layers in the first and
second isolation trenches.
The closest prior arts on record are Said et al. (US 2024/0105622 A1) and Kim et al. (US 2022/0336421 A1). However, none of the existing prior arts on record teaches nor would be obvious to add such an element with and obvious motivation or breaking the functionality of the device.
Claims 19-25 are also allowed being dependent on allowable claim 18.
Claims 3-4 and 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897