DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is responsive to the amendment and remarks received November 19, 2025. Claims 10-20 are canceled. No claims are amended or newly added. Claims 1-9 are currently pending.
Election/Restrictions
Applicant’s election of Invention I, claims 1-9, in the reply filed on November 19, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant has canceled the non-elected claims, so no claims are withdrawn from consideration.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings were received on August 24, 2023. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Haase et al. (US Patent Application Publication 2024/0019638, hereinafter referred to as “Haase”). Haase anticipates claims:
1. A silicon photonics structure, comprising a silicon photonics device, wherein the silicon photonics device (see figures 1-15)33 comprises:
a substrate having a first side (see figure 1A, the left side of all the structures shown are interpreted as the first side) and a second side (see figure 2A, the side of recess 15 opposite the waveguides 20a is interpreted as the second side) opposite to each other, wherein a width of the first side is greater than a width of the second side (see figure 2A, the width of the second side is only a small portion of the width of the first side, thereby meeting this limitation), and the substrate comprises a staircase structure (see figure 2A, the depression of the recess 15 to the flat, top surface of 10a is interpreted as a staircase structures); and
a waveguide (20a) located on the first side.
2. The silicon photonics structure according to claim 1,
wherein the staircase structure comprises a first step (the step up to the top surface of 10a from the recess 15 is interpreted as the first step),
a second step (the step up onto support portion 31 is interpreted as the second step), and
a third step (the step up onto optical ferrule 50 is interpreted as the third step),
the first step is adjacent to the first side, the third step is adjacent to the second side, and the second step is located between the first step and the third step (see figure 1A).
3. The silicon photonics structure according to claim 2,
wherein the first step comprises a first sidewall (the sidewall of recess 15 is interpreted as the first sidewall) and a first tread (the top flat surface of 10a that is under portion 30 is interpreted as the first tread),
the first sidewall is connected to the first side (see figure 1A),
the first tread is connected to the first sidewall,
the second step comprises a second sidewall (the side of 30 is interpreted as the second sidewall) and a second tread (the top of 30 is interpreted as the second tread), the second sidewall is connected to the first tread, the second tread is connected to the second sidewall, the third step comprises a third sidewall (the side of 50 is interpreted as the third sidewall) and a third tread (the top of 50 is interpreted as the third tread), the third sidewall is connected to the second tread, and the third tread is connected to the third sidewall (see figure 1A).
4. The silicon photonics structure according to claim 3, wherein a width of the third tread is greater than a width of the second tread, and the width of the second tread is greater than a width of the first tread (see figure 1A).
5. The silicon photonics structure according to claim 3, wherein a height of the second sidewall is greater than a height of the first sidewall, and the height of the first sidewall is greater than a height of the third sidewall (see figure 15, this limitation is met by the heights in the direction from the right of the page to the left of the page).
6. The silicon photonics structure according to claim 2, further comprising: an optical fiber device (waveguide 23 is interpreted as the optical fiber device) located on one side of the waveguide and one side of the first step (see figure 1).
7. The silicon photonics structure according to claim 6, wherein the optical fiber device comprises an optical fiber array (see figure 1A).
8. The silicon photonics structure according to claim 6, further comprising: an adhesive layer located between the first step and the optical fiber device (see paragraph 0058).
9. The silicon photonics structure according to claim 1, wherein the silicon photonics device further comprises: an insulating layer (optical material 26 is interpreted as an insulating layer, see figure 7) located between the waveguide and the substrate (see figure 7); and
a cladding layer (the air surrounding the structures is interpreted as the cladding layer) located on the waveguide and the insulating layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M BEDTELYON whose telephone number is (571)270-1290. The examiner can normally be reached 8:00am - 4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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/John Bedtelyon/Primary Examiner, Art Unit 2874