DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 03/04/2026 is acknowledged. Claims 16-20 are hereby withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/24/2023 and 8/12/2024 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-7, 11-12, 14-15 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yeh (US 20210305802 A1)
Regarding claim 1, Yeh discloses (Fig. 3A) An integrated circuit device comprising:
a backside power distribution network structure (BSPDNS) (conductive structures 340, 344, 346);
a logic device region (Clamp 310) and a passive device region (D1 (302) on the BSPDNS;
a backside insulating layer (321) comprising a first portion extending between the BSPDNS and the logic device region and a second portion extending between the BSPDNS and the passive device region,
the passive device region comprising a semiconductor layer (well 322) that is in the backside insulating layer; and
a dam (STI 328b, 328c) separating the first portion of the backside insulating layer from the semiconductor layer of the passive device region.
Regarding claim 2, Yeh discloses (Fig. 3A) The integrated circuit device of Claim 1, further comprising a first backside contact (344) in the backside insulating layer, wherein the first backside contact is electrically connected to a source/drain region (310a, [0121]) of the logic device region.
Regarding claim 4, Yeh discloses the integrated circuit device of Claim 2, further comprising a second backside contact (340) in the backside insulating layer, wherein the semiconductor layer comprises a region including impurities (324), and wherein the second backside contact is electrically connected to the region including the impurities ([0125]).
Regarding claim 5, Yeh discloses the integrated circuit device of Claim 4, wherein a lower surface of the first backside contact is coplanar with a lower surface of the second backside contact (Fig. 3A).
Regarding claim 6, Yeh discloses the integrated circuit device of Claim 4, wherein a thickness of the first backside contact is greater than a thickness of the second backside contact (Fig. 3A).
Regarding claim 7, Yeh discloses the integrated circuit device of Claim 1, wherein a portion of the dam is in the backside insulating layer, and wherein a thickness of the portion of the dam is thinner than a thickness of the first portion of the backside insulating layer (Fig. 3A).
Regarding claim 11, Yeh discloses (Fig. 3A) An integrated circuit device comprising:
a backside power distribution network structure (BSPDNS) (conductive structure 340, 344, 346);
a first device region (clamp 310) and a second device region (D1 (302)) on the BSPDNS;
a backside insulating layer (321) extending between the BSPDNS and the first device region and between the BSPDNS and the second device region,
the second device region comprising a semiconductor layer (well 322) that is in the backside insulating layer; and
a dam (STI 328c) that is at least partially in the backside insulating layer, wherein the dam extends between the backside insulating layer and a side surface of the semiconductor layer (Fig. 3A).
Regarding claim 12, Yeh discloses (Fig. 3A) The integrated circuit device of Claim 11, wherein a thickness of a portion of the backside insulating layer, which extends between the BSPDNS and the first device region (distance from lower end of 310 to lower end of 344), is thicker than a thickness of a portion of the backside insulating layer, which extends between the BSPDNS and the second device region (distance from lower end of 322 to lower end of 340).
Regarding claim 14, Yeh discloses (Fig. 3A) The integrated circuit device of Claim 11, further comprising:
a first backside contact (344) electrically connected to the BSPDNS and a source/drain region of the first device region; and
a second backside contact (340) electrically connected to the BSPDNS and the semiconductor layer.
Regarding claim 15, Yeh discloses (Fig. 3A) The integrated circuit device of Claim 14, wherein a lower surface (lower end of 344) of the first backside contact is coplanar with a lower surface (lower end of 340) of the second backside contact, and
wherein a distance between an upper surface (lower end of contacts) of the BSPDNS and a lower surface of the semiconductor layer is longer than or equal to a distance between the upper surface of the BSPDNS and a lower surface of the dam.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US 20210305802 A1) in view of Orr (US 20220415877 A1)
Regarding claim 8, Yeh discloses (Fig. 3A) the semiconductor layer extends between the diode 302 with cathode and anode terminals. Yeh does not disclose the diode having source/drain layer.
Orr discloses (Fig. 1A) an analogous art of diode 101 facilitating ESD protection to transistors formed above the diode 101 (¶ [0068]). Orr discloses in ¶ [0038] disclosing “integration schemes that can co-fabricate transistors alongside an ESD protection device by utilizing fin structures as source and drain for respective transistors and doped fin structures as terminals of diodes can provide significant process advantages and offer cost benefits. Cost savings can stem from a lack of a need to implement separate masks for forming terminals of the diode by utilizing fin patterning to simultaneously form fins and terminals for transistors and one or more diodes, respectively, for example.”
Thus, one of ordinary skill in the art before the filling date of the invention would have substitute the diode of Yeh for the Finfet diode of Orr for cost saving.
The modified diode of Yeh by Orr would result for the semiconductor layer being between the source/drain layer and the second portion of the insulating layer.
Claim(s) 3, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh (US 20210305802 A1) in view of Orr (US 20220415877 A1) and Wang (US 20210391320 A1)
Regarding claim 3, Yeh discloses (Fig. 3A) The integrated circuit device of Claim 2, wherein the dam is between the first portion of the backside insulating layer and the semiconductor layer in a direction parallel to an upper surface of the BSPDNS.
Yeh is silent regarding an upper surface of the dam is coplanar with an upper surface of the first backside contact.
Yeh discloses the diode formed in the backside insulating layer to be connected to a diode with cathode and anode. Orr discloses (Fig. 1A and ¶ [0068]) such a diode can be formed by a FinFet diode where source/drain of the transistors are utilized for diode terminals for cost saving. Thus, one of ordinary skill in the art before the filling date of the invention would have substituted the diode of Yeh for the Finfet diode of Orr for cost saving.
The modification of the Yeh diode by Orr would result for the circuit and diode regions of the device being under multiple fins of transistors. Yeh’s device modified by Orr would result for the STI trench being realized by using one of the trenches between the fins as revealed by Wang below.
Wang discloses (Fig. 10A, ¶ [0038]) forming the bottom source/drain layer (252) by extending downwardly a source trench (246) between fins (232) to reserve a space for backside source/drain contact. Thus, one of ordinary skill in the art before the time of the invention would have realized the source/drain trench extension for backside contact can be used to separate the circuit region and the diode region. The STI trench in Yeh device can be realized by the existing source/drain trench extension for cost saving. The modification to the STI trench of Yeh would result for the trench upper surface being below the fins, in other words, co-planar with the upper surface of the fist backside contact.
Regarding to claim 13, Yeh discloses the integrated circuit device of Claim 11, but is silent regarding the dam has a round lower surface. Similarly presented in claim 3, the dam (trench realized from the source/drain trench downward extension as disclosed by Wang) has a round lower surface.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cheng (US 9991254 B1) disclosing forming a FET and a BJT areas using nanosheets. Drowley discloses forming an active region and a body diode region separating by an isolation region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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/DTH/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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