DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 02/20/2024.
Claims 1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statements (IDS) filed on 11/23/2023, and 02/20/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-7, and 11-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lai et al. (US 2022/0336325)
Regarding claim 1, Lai discloses an electronic device, comprising:
a substrate 203 (see fig. 2A);
a first semiconductor device 202 comprising a first plurality of gate all-around (GAA) field effect transistors (FETs) (having channel bar 205, see para. 0028; see also paras. 0019, 0096) formed over a first (upper) side of the substrate 203;
a second semiconductor device 204 comprising a second plurality of GAA FETs (having channel bar 209, see para. 0028; see also paras. 0019, 0096) formed over a second (lower) side of the substrate, opposite the first side; and
a power supply structure 217 disposed at the first side, the power supply structure 217 configured to supply power to one or more of: (i) the first plurality of GAA FETs 202 through first electrical couplings (similar to electrical coupling 213 connecting a power supply 215 at the bottom of the device to the second semiconductor device 204; see fig. 2A) disposed at the first side (upper side), and (ii) the second plurality of GAA FETs through second electrical couplings comprising one or more inter-side vias (ISVs) traversing the substrate from the second side to the first side (see also para. 0015: power rail at one side can be linked to power rail at the other side of the substrate).
Regarding claim 2, Lai discloses the electronic device according to claim 1, wherein at least a given ISV 329 (fig. 3A) among the ISVs comprises an electrically conductive interconnect 329, the electrically conductive interconnect being formed within the given ISV and being configured to conduct an electrical signal 328 between the first and second semiconductor devices. See fig. 3A.
Regarding claim 3, Lai discloses the electronic device according to claim 2, wherein at least one of the power supply structure 217 (in fig. 2A) or 310 (in fig. 3A), the first semiconductor device 202 (fig. 2A) or 301 (fig. 3A), and the second semiconductor device 204 or 303 is configured to conduct, through the given ISV 329, at least one of: (i) a data signal, (ii) a power signal, and (iii) a ground signal. See fig. 3A (see also para. 0015: power rail at one side can be linked to power rail at the other side of the substrate).
Regarding claim 4, Lai discloses the electronic device according to claim 1, further comprising an additional power supply structure 215 (fig. 2A) or 324 (fig. 3A) disposed at the second side, the additional power supply structure 215/324 (fig. 2A/fig. 3A) being configured to supply power to one or more of: (i) the second plurality of GAA FETs 204/303 through the second electrical couplings 213/322 disposed at the second side, and (ii) the first plurality of GAA FETs 202/301 through the first electrical couplings 308 (fig. 3A) and at least the one or more ISVs of the second electrical couplings.
Regarding claim 5, Lai discloses the electronic device according to claim 1, wherein the first semiconductor device 202 comprises a first type of semiconductor device, and the second semiconductor device 204 comprises a second type of semiconductor device. See fig. 2A, and paras. 0027-0038.
Regarding claims 6, and 7, Lai discloses the electronic device according to claim 5, wherein the first and second types of semiconductor devices comprise a same type of semiconductor device, or different types of semiconductor devices. These are inherent features and would involve only routine skills in the art to select suitable conductivity types for the device, and it would depend upon the choice of the designer and/or the application of the device.
Regarding claim 11, Lai discloses a method for fabricating an electronic device, the method comprising:
forming, on a first (upper) side of a substrate 203 (see fig. 2A), a first semiconductor device 202 comprising a first plurality of gate all-around (GAA) field effect transistors (FETs) (having channel bar 205, see para. 0028; see also paras. 0019, 0096);
forming, on a second side (lower) of the substrate 203 that is opposite the first side, a second semiconductor device 204 comprising a second plurality of GAA FETs (having channel bar 209, see para. 0028; see also paras. 0019, 0096); and
disposing at the first side, a power supply structure 217 for supplying power to one or more of: (i) the first plurality of GAA FETs through first electrical couplings (similar to electrical coupling 213 connecting a power supply 215 at the bottom of the device to the second semiconductor device 204; see fig. 2A) disposed at the first side, and (ii) the second plurality of GAA FETs through second electrical couplings comprising one or more inter-side vias (ISVs) traversing the substrate from the second side to the first side (see also para. 0015: power rail at one side can be linked to power rail at the other side of the substrate).
Regarding claim 12, Lai discloses the method according to claim 11, further comprising forming within at least a given ISV 329 (fig. 3A) among the ISVs, an electrically conductive interconnect 329 for conducting an electrical signal between the first and second semiconductor devices. See fig. 2A, fig. 3A.
Regarding claim 13, Lai discloses the method according to claim 12, wherein forming the electrically conductive interconnect 329 is for conducting, from at least one of the power supply structure, the first semiconductor device and the second semiconductor device, and through the given ISV, at least one of: (i) a data signal, (ii) a power signal, and (iii) a ground signal. See fig. 2A, fig. 3A.
Regarding claim 14, Lai discloses the method according to claim 11, further comprising disposing at the second side (lower side), an additional power supply structure 215 (fig. 2A) or 324 (fig. 3A) for supplying power to one or more of: (i) the second plurality of GAA FETs 204/303 through the second electrical couplings 213/322 disposed at the second side, and (ii) the first plurality of GAA FETs 202/301 through the first electrical couplings 308 (fig. 3A) and at least the one or more ISVs of the second electrical couplings.
Regarding claim 15, Lai discloses the method according to claim 11, wherein forming the first semiconductor device 202 comprises forming a first type of semiconductor device, and forming the second semiconductor device 204 comprises forming a second type of semiconductor device. See fig. 2A, and paras. 0027-0038.
Regarding claims 16, and 17, Lai discloses the method according to claim 15, wherein forming the first and second types of semiconductor devices comprises forming a same type of semiconductor device, or forming different types of semiconductor devices. These are inherent features and would involve only routine skills in the art to select suitable conductivity types for the device, and it would depend upon the choice of the designer and/or the application of the device.
Claim Rejections - 35 U.S.C. § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 8-10, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 2022/0336325).
Regarding claims 8-10, Lai discloses the electronic device according to claim 1, comprising all claimed limitations, as discussed above, except for specifically teach that
wherein the substrate comprises a non-conductive substrate, wherein the non-conductive substrate comprises a ceramic substrate, and/or wherein the non-conductive substrate comprises a polymer substrate.
However, it would have been obvious to one of ordinary skills in the art at the time the invention was made that the substrate of Lai can be of any suitable material, including a non-conductive substrate, and that selecting a known material on the basis of its suitability for the intended use is just within the general skill of a worker in the art.
MPEP § 2144.07 states that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol; “Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle.” 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of aknown plastic to make a container of a type made of plastics prior to the invention washeld to be obvious); Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323(Fed. Cir. 1988) (Claimed agricultural bagging machine, which differed from a prior art machine only in that the brake means were hydraulically operated rather than mechanically operated, was held to be obvious over the prior art machine in view of references which disclosed hydraulic brakes for performing the same function, albeit in a different environment.).
Caterpillar Inc. v. Deere & Co., 224 F.3d 1374, 56USPQ2d 1305 (Fed. Cir. 2000); Al-Site Corp. v. VSI Int ’ l, Inc., 174 F.3d 1308, 1316, 50 USPQ2d 1161, 1165 (Fed. Cir. 1999); Chiuminatta Concrete Concepts, Inc. v. Cardinal Indus. Inc., 145 F.3d 1303, 1309, 46 USPQ2d 1752, 1757 (Fed. Cir. 1998); Lockheed Aircraft Corp. v. United States , 193 USPQ 449, 461 (Ct. Cl. 1977 ); Data Line Corp. v. Micro Technologies, Inc., 813 F.2d 1196, 1 USPQ2d 2052 (Fed. Cir. 1987). In re Leshin, 125 USPQ 416.
See also MPEP § 2183.
Regarding claims 18-20, Lai discloses the method comprising all claimed limitations. See the rejections of claims 8-10.
Conclusion
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 February 17, 2026