Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to application 18/455083 filed on 08/24/23.
Summary of claims
Claims 1-20 are pending.
Claims 1-20 are rejected.
Oath/Declaration
The oath/declaration filed on August 24th, 2023 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeh et al. (US Pub. 2010/0241414).
As to claim 1 the prior art teaches a computer-implemented method for instrumentation-assisted debugging, the computer-implemented method comprising:
compiling a hardware design to generate a compiled design (see fig 1-3 paragraph 34-36);
generating, from the compiled design, code for the hardware design and debug assist elements (see fig 1-5 paragraph 36-42);
feeding the code into a vendor emulation flow that outputs a vendor waveform (see fig 4-7 paragraph 41-46);
and transforming the vendor waveform into a logic simulation waveform compatible with a hardware design language (HDL) using the debug assist elements for hardware logic debugging (see fig 4-8 paragraph 45-51).
As to claim 2, 9 and 16 the prior art teaches wherein the hardware design is generated from mixed-language sources (see fig 1-3 paragraph 0033-0035).
As to claim 3, 10 and 17 the prior art teaches wherein the compiling is executed by a register transfer level (RTL) compiler (see fig 1-3 paragraph 0008-0010 and 0033).
As to claim 4, 11 and 18 the prior art teaches wherein the code for the hardware design is a hardware description language (HDL) (see fig 5-7 paragraph 0041-0044).
As to claim 5, 12 and 19 the prior art teaches wherein the vendor emulation flow comprises a vendor compiling operation, a vendor emulation operation and a vendor waveform generation operation of multiple vendors (see fig 5-7 paragraph 0042-0045).
As to claim 6 and 13 the prior art teaches wherein the generating of the debug assist elements comprises adding one or more extensions to a platform for executing the computer-implemented method (see fig 5-7 paragraph 0038-0043).
As to claim 7, 14 and 20 the prior art teaches wherein the one or more extensions are configured to extract and store type information that can be augmented into the logic simulation waveform (see fig 8-10 paragraph 0054-0057).
As to claim 8 the prior art teaches a computer program product for instrumentation-assisted debugging, the computer program product comprising one or more computer readable storage media having computer readable program code collectively stored on the one or more computer readable storage media, the computer readable program code being executed by a processor of a computer system to cause the computer system to perform a method comprising:
compiling a hardware design to generate a compiled design (see fig 1-3 paragraph 34-36);
generating, from the compiled design, code for the hardware design and debug assist elements (see fig 1-5 paragraph 36-42);
feeding the code into a vendor emulation flow that outputs a vendor waveform (see fig 4-7 paragraph 41-46);
and transforming the vendor waveform into a logic simulation waveform compatible with a hardware design language (HDL) using the debug assist elements for hardware logic debugging (see fig 4-8 paragraph 45-51).
As to claim 15 the prior art teaches a computing system comprising: a processor; a memory coupled to the processor; and one or more computer readable storage media coupled to the processor, the one or more computer readable storage media collectively containing instructions that are executed by the processor via the memory to cause the processor to perform steps for instrumentation-assisted debugging comprising:
compiling a hardware design to generate a compiled design (see fig 1-3 paragraph 34-36);
generating, from the compiled design, code for the hardware design and debug assist elements (see fig 1-5 paragraph 36-42);
feeding the code into a vendor emulation flow that outputs a vendor waveform (see fig 4-7 paragraph 41-46);
and transforming the vendor waveform into a logic simulation waveform compatible with a hardware design language (HDL) using the debug assist elements for hardware logic debugging (see fig 4-8 paragraph 45-51).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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