Prosecution Insights
Last updated: April 19, 2026
Application No. 18/455,411

MEMORY DEVICE

Non-Final OA §103
Filed
Aug 24, 2023
Examiner
BRADFORD, PETER
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
84%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
586 granted / 733 resolved
+11.9% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
42 currently pending
Career history
775
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
41.1%
+1.1% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
32.5%
-7.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 733 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restriction The applicant elects invention I with traverse. “In this day and age of high-powered computing, well-networked information database, and artificial intelligence, the applicant just cannot comprehend how the relevant information database can be ‘ very large, ’ unless the Office expects manual search used to be performed long ago. The USPTO rules require that the examiners must examine claims on the merits if the burden isn't serious, even for independent or distinct inventions, with MPEP § 808.02 The present office action had indeed acknowledged the overlap between the two groups. This further supports that a restriction would not provide a meaningful reduction in examination burden. These overlapping groups do not unreasonably increase the scope of search.” The applicant’s comments are in apropos . The question is not whether the documents must be thumbed through on paper , but rather the number of references that must be searched through , reviewed and considered. The relevant scope of the type of memory device is very large; they cannot reasonably all be considered. The two inventions are largely non-overlapping, and thus are essentially two separate searches, which require different search strategies and consideration , and it is not reasonable to conduct both searches in one application. There will be overlap between any memory device; the existence of overlap does not make them unrestrictable . The restriction requirement is made final, and claims 9-14 are withdrawn from consideration. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes MEMORY WITH SOURCE STRUCTURE HAVING A PROTRUSION The specification uses two different terms (2P and P2) for what appears to be the same element: “ the second part 2P of the insulating pattern IP ” [0053]; “ the second part P2 of the insulating pattern IP ” [0070] . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Choi, US 2020 / 0258901 A1 , in view of Jae Taek Kim, US 2020 / 0273881 A1 , and Choasub Kim, US 2024 / 0164091 A1 . Claim 1: Choi discloses a source structure (SL2, FIG. 3B) including a top surface extending along a first direction and a second direction (II and III) , which intersect each other . Choi discloses support structures 131 which create a shape around them including protrusions (FIG. 5). Choi discloses that the slit SI1 goes into the source structure SL (FIG. 3B), but does not specifically show the support structures penetrating into the source structure. However, this was known in the art. See Choasub Kim, FIG. 1, showing supports SUS penetrating the source structure SST : See also Jae Taek Kim, support VB penetrating source structure SL : It would have been obvious to have had the support structure penetrate the source structure as known in the art e.g. in order to have adequate support, and to facilitate formation of source structure using a sacrificial source structure (Jae Taek Kim, [0117]-[0119]). In Choi in view of Jae Taek Kim or Choasub Kim, the support structures 131 and plugs 153 would exist in the source structure, and thus the connection region AR2 of Choi FIG. 5 would have the same structure in the source structure. Thus: the source structure including a concave part and a protrusion part (portions of 131, FIG. 5/SI E , FIG. 3B) , which are alternately disposed along the first direction; a contact plug (151) spaced apart from a sidewall of the source structure, the contact plug facing the concave part; and a gate stack structure including a plurality of insulating layers (101) and a plurality of conductive layers (WL/103) , which are alternately disposed over the source structure, wherein the protrusion part of the source structure protrudes farther in the second direction than the concave part of the source structure. Claim 2: Choi discloses a first support structure (131 C ) disposed over the source structure, the first support structure having a first support part corresponding to the concave part of the source structure and a second support part (131 B ) corresponding to the protrusion part of the source structure, wherein the second support part of the first support structure has a width wider than a width of the first support part of the first support structure in the second direction. Claim 3: Choi discloses a second support structure (131A) facing the first support part of the first support structure; and a gate contact (151) facing the second support part of the first support structure, the gate contact being in contact with one conductive layer among the plurality of conductive layers ([0095]) . Claim 4: the first support structure and the second support structure include an insulating material ([0078]) . Claim 5: the source structure includes a first source structure and a second source structure, and wherein the first source structure and the second source structure are spaced apart from each other with the contact plug interposed therebetween. Claim 6: an insulating pattern (Jae Taek Kim, LIL2, FIG. 3A), surrounding the contact plug is disposed between the first source structure and the second source structure. Claim 8: Choi discloses a peripheral circuit disposed under the source structure, the peripheral circuit being electrically connected to the contact plug (FIG. 2) . Allowable Subject Matter Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The particular structure of the insulating pattern claimed, in light of the other claimed structure, was not found by the examiner. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited : Noh, US 20220246638 A1 , FIG. 1, shows some structures similar to the present application. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT PETER BRADFORD whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1596 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 10:30-6:30 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Jacob Choi can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 469.295.9060 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER BRADFORD/ Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Aug 24, 2023
Application Filed
Mar 24, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604477
SEMICONDUCTOR DEVICE WITH CONDUCTIVE LAYERS IN ISOLATION STRUCTURES
2y 5m to grant Granted Apr 14, 2026
Patent 12604585
MICROLED CONNECTION WITH CU BUMP ON TI/AL WIRE
2y 5m to grant Granted Apr 14, 2026
Patent 12593573
DISPLAY DEVICE COMPRISING A DISPLAY PANEL HAVING INSULATING LAYERS OVER A PAD AND METHOD OF PROVIDING THE DISPLAY PANEL
2y 5m to grant Granted Mar 31, 2026
Patent 12581658
FERROELECTRIC MEMORY WITH MULTIPLE FERROELETRIC LAYERS THROUGH A STACK OF GATE LINES
2y 5m to grant Granted Mar 17, 2026
Patent 12575429
SEMICONDUCTOR PACKAGE HAVING A LEAD FRAME AND A CLIP FRAME
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
84%
With Interview (+4.1%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 733 resolved cases by this examiner. Grant probability derived from career allow rate.

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