Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I: Claims 1-19 in the reply filed on 12/17/2025 is acknowledged. The traversal is on the ground(s) that that paragraph [0067] of the specification defines “fabricating a core” as a manner of “providing a core,” thereby making the e processes functionally identical. This argument is unpersuasive as it relies on the specification rather than the limitations of the claims.
Under MPEP § 806.05(f), to maintain a restriction between a product an da process of making it, the Examiner must show that the product can be made by a “materially different process.”
While the specification at [0067] describes one method of providing a core (involving resin encapsulation and curing), the product defined in Group I only requires that a core be “provided.” This core could be produced by several material different processes not recited in Group II, even when limiting the term “providing” to the argued definition at [0067], such as:
1: Alternative Implementation Methods: Paragraph [0067] states “in some implementations, providing the core includes…” the recited steps. This qualifier confirms that there are other implementations of the product where the core is “provided” without performing the specific fabrication sequence of Invention II as argued as defined by paragraph [0067].
2: Alternative Fabrication Methods: The core structure of Invention I can be “provided” via materially different processes such as subtractive laser drilling/etching of pre-formed dielectric or injection molding, neither of which require the specific resin application and curing sequence recited in paragraph [0067] and argued to be understood in the reading of “providing” the claim.
3: Common Usage of “providing”: Under broadest reasonable interpretation (BRI), “providing” may include the common definition of simply providing a store-bought, off-the-shelf component. A core obtained from a 3rd party vendor is “provided” to the assembly process but is not “fabricated” by the specific process steps of Invention II.
As addressed above and provided for in the Restriction Requirement, the inventions are distinct because Invention I is directed to a assembled device structure and Invention II is directed to a method of manufacturing process. These involve different fields of search, different fields of classification, and/or have divergent subject matter. The examination of both would place undue burden on the Office.
Because the product of Invention I can be made by materially different process from the Invention II, the inventions are distinct. The requirement is still deemed proper and is therefore made FINAL. Claims 20-30 are withdrawn from further consideration under 37 CFR 1.142(B) as directed to a non-elected invention.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 9, 11-15, 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mikado et al. (US 20120188734 A1).
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CLAIM 1. Mikado discloses in Fig. 1 and related text a device comprising:
a core 102+100+101 comprising:
an upper core dielectric layer 101;
a lower core dielectric layer 102;
a central core dielectric layer 100 in direct contact with a bottom surface of the upper core dielectric layer and in direct contact with a top surface of the lower core dielectric layer; and
a passive electronic component 2001 embedded within the central core dielectric layer 100 (Mikado et al. ¶137);
an upper laminate stack 11+110 coupled to a top surface of the upper core dielectric layer 101 and comprising:
a set of upper metal layers 110; and
a set of contact pads P1 [Note: Openings shown are understood to pad location analogous to P1.] configured to electrically connect a die [Note: this is a statement of intended purpose and does not necessarily require a die.] to the passive electronic component 200 by way of conductive paths 311 defined by the set of upper metal layers 110; and
a lower laminate stack 12+120 coupled to a bottom surface of the lower core dielectric layer 102 and comprising:
a set of lower metal layers 120 including a first lower metal layer 121 directly in contact with the bottom surface of the lower core dielectric layer 102; and
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a set of lower dielectric layers 12 disposed between adjacent metal layers of the set of lower metal layers (See mark-up fig. 1, highlighting each dielectric layer portion 12 located between adjacent layers of the set of lower metal layers.).
Alternatively, as illustrated in Figure 29 of Mikado, multiple art-recognized built-up layers may be disposed over the primary upper 110 or lower 120 metal layers, thereby situating a set of dielectric insulating layers 103 vertically between metallization levels 110 and 130. The implementation of these addition metallization build-up layers (110+103+130+11) demonstrates a predictable application of known elements by a POSITA prior to the time of the invention. Such modification to the device of Mikado would be a matter of routine design choice or technical necessity to achieve higher density conductive line routing and/or increased circuit complexity. This modification provides only the expected results of enhanced vertical integration, making the additional layers obvious to a POSITA at the time of the invention. See MPEP 2144.04.
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CLAIM 2. Mikado et al. discloses a device of claim 1, wherein the upper laminate stack further comprises a set of upper dielectric layers disposed between adjacent metal layers of the set of upper metal layers (Mikado Fig. 1 & 29 – See claim 1 build-up metallization layers for vertical integration.).
CLAIM 3. Mikado et al. discloses a device of claim 1, wherein the set of upper metal layers includes a first upper metal layer 110 directly in contact with the top surface of the upper core dielectric layer 101 (Mikado Fig. 1 & 29 – See claim 1 build-up metallization layers for vertical integration.).
CLAIM 4. Mikado et al. discloses a device of claim 1, wherein the set of lower metal layers includes a first lower metal layer 120 directly in contact with the bottom surface of the lower core dielectric layer 102 (Mikado Fig. 1 & 29 – See claim 1 build-up metallization layers for vertical integration.).
CLAIM 5. Mikado et al. discloses a device of claim 1, wherein a metal layer closest to the core among the set of lower metal layers includes one or more traces that pass through a shadow of the passive electronic component (Mikado Fig. 1 & 29).
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CLAIM 6. Mikado et al. discloses a device of claim 1, wherein the passive electronic component includes an integrated capacitor device (Mikado ¶137, Fig. 1 & 29).
CLAIM 9. Mikado et al. discloses a device of claim 1, further comprising a plurality of conductive vias 300 extending through the core 100 and electrically interconnecting the set of upper metal layers 110 and the set of lower metal layers 120 (Mikado Fig. 1).
CLAIM 11. Mikado et al. discloses a device comprising:
a core 100 including a passive electronic component 100 (Mikado ¶137) embedded therein;
an upper laminate stack coupled to the core and comprising a set of contact pads configured to electrically connect a die (Note: Statement of purpose, not positively requiring a die.) to the passive electronic component by way of conductive paths defined by one or more upper metal layers of the upper laminate stack (Mikado figs. 1 & 29 – See claim 1 regarding one or more upper metal layers); and
a lower laminate stack coupled to the core and comprising a set of lower metal layers (Mikado fig. 1); wherein a metal layer closest to the core among the set of lower metal layers includes one or more traces that pass through a shadow of the passive electronic component (Mikado figs. 1 & 29 – See claim 1 regarding one or more upper metal layers).
CLAIM 12. Mikado et al. discloses a device of claim 11, wherein the upper laminate stack further comprises a set of upper dielectric layers disposed between adjacent metal layers of the set of upper metal layers 110 (Mikado fig. 1 – see regarding claim 1).
CLAIM 13. Mikado et al. discloses a device of claim 11, wherein the set of upper metal layers includes a first upper metal layer 110 directly in contact with a top surface of an upper core dielectric layer 101 of the core (Mikado fig. 1).
CLAIM 14. Mikado et al. discloses a device of claim 11, wherein the metal layer closest to the core among the set of lower metal layers 120 contacts a bottom surface of a lower core 102 dielectric layer of the core (Mikado fig. 1).
CLAIM 15. Mikado et al. discloses a device of claim 11, wherein the passive electronic component includes a capacitor device (Mikado ¶137).
CLAIM 17. Mikado et al. discloses a device of claim 11, further comprising one or more additional components (Mikado et al. ¶137) electrically connected to the die via the conductive paths defined by the set of upper metal layers (See regarding claim 7, It would be obvious to a POSITA to connect a die to the upper metal layers that connect to the buried component. Per paragraph 137, the component may may comprise various internal components (IC and/or passive components), thus the would be connected to the overall device circuit by the metal layers.).
CLAIM 18. Mikado et al. discloses a device of claim 11, further comprising a plurality of conductive vias 300 extending through the core 100 to interconnect the set of upper metal layers 110 and the set of lower metal layers 120 (Mikado Fig. 1).
Claim(s) 7-8, 10, 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mikado et al. (US 20120188734 A1) in view of Lee et al. (US 20140182896 A1).
CLAIM 7. While Mikado discloses the device of claim 1, it fails to explicitly disclose the die as part of the integrated device structure. However, Lee et al. teaches an analogous structure featuring a core board with a buried passive device and overlying build-up metallization layers that further comprise a die (Lee ¶[0007-0008]). In Lee, the power distribution network of the die is coupled to the passive electronic component via contact pads and conductive paths defined by upper metal layers.
Lee specifically teaches that this buried configuration allows the die’s power distribution network to be coupled to the passive component through relatively shorter conductive paths. A POSITA would have been motivated to include a die as taught by Lee and specifically couple its power distribution network to the passive component (e.g., capacitor) closer to the die.
Therefore, it would have been obvious to a POSITA at the time of the invention to modify the device of Mikado to include a die coupled to the passive element. Applying a known technique (Lee’s die integration) to a known device ready for improvement (Mikado’s buried passive structure) to yield predictable results (reduced inductance) is a rationale for obviousness under KSR International Co. v. Teleflex INC., 550 U.S. 398 (2007).
CLAIM 8. Mikado et al. discloses a device of claim 7, further comprising one or more additional components (Mikado et al. ¶137) (electrically connected to the die via the conductive paths defined by the set of upper metal layers (See regarding claim 7, It would be obvious to a POSITA to connect a die to the upper metal layers that connect to the buried component. Per paragraph 137, the component may may comprise various internal components (IC and/or passive components), thus the would be connected to the overall device circuit by the metal layers.).
CLAIM 10. Mikado et al. discloses a device of claim 1, however may be silent upon further comprising a set of ball grid array (BGA) contacts on a bottom surface of the lower laminate stack and configured to electrically connect the device to another device or substrate, wherein at least one BGA contact of the set of BGA contacts is positioned at least partially within a shadow of the passive electronic component.
As addressed regarding claim 7, it would be obvious to a POSITA at the time of the inventio to further connect a die to the upper metallization layers as demonstrated in Lee et al. (See Regarding claim 7). As further demonstrated by Lee et al. such connections are conventionally accomplished by solder balls (e.g. a BGA (ball grid array).
Connecting a die to the device disclosed in Mikado et as addressed regarding claim 7 would be recognized to further comprise a set of ball grid array (BGA) contacts 191 (Fig. 3 Lee et al.) on a bottom surface of the lower laminate stack and configured to electrically connect the device to another device or substrate, wherein at least one BGA contact of the set of BGA contacts is positioned at least partially within a shadow of the passive electronic component.
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CLAIM 16. Mikado et al. teaches device of claim 11, Lee et al. further comprising the die, wherein a power distribution network of the die is coupled, via the set of contact pads and the conductive paths defined by the set of upper metal layers to the passive electronic component (See regarding claim 7 for discussion regarding the motivation and rationale for the combination of Mikado and Lee as applied.)
CLAIM 19. Mikado et al. teaches device of claim 11, Lee et al. further comprising a set of ball grid array (BGA) contacts on a bottom surface of the lower laminate stack and configured to electrically connect the device to another device or substrate, wherein at least one BGA contact of the set of BGA contacts is positioned at least partially within the shadow of the passive electronic component (See regarding claim 10 for discussion regarding the motivation and rationale for the combination of Mikado and Lee as applied.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
1/15/2025
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 [0137] Electronic component 200 is not limited to a specific type. Any electronic component, for example, an active component such as an IC circuit along with a passive component such as a capacitor, resistor or inductor, may be used. As shown in FIG. 30, for example, electronic component 200 containing an IC chip may be positioned in cavity (R10) of substrate 100, and fixed using an insulator (adhesive agent (200b) and insulator (101a)). In the example shown in FIG. 30, electronic component 200 has pad (200a) on its fourth-surface (F4) side, and fourth surface (F4) of electronic component 200 is covered by adhesive agent (200b) (adhesive layer). In addition, conductive layer 120 has conductive pattern (PT1) positioned on substrate 100 and conductive pattern (PT2) positioned on the insulative material (adhesive agent (200b) and insulator (101a)) filled in cavity (R10). Pad (200a) of electronic component 200 and conductive pattern (PT2) are electrically connected to each other by the conductor in a via hole formed in adhesive agent (200b) (via conductor 200c). Adhesive agent (200b) is used to fix the IC chip (electronic component 200) to a support sheet during a manufacturing process, for example.