Prosecution Insights
Last updated: July 17, 2026
Application No. 18/455,447

PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF, MEMORY SYSTEM AND ELECTRONIC APPARATUS

Non-Final OA §102§103
Filed
Aug 24, 2023
Priority
May 10, 2023 — CN 202310528102X
Examiner
PROSTOR, ANDREW VICTOR
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
1 (Non-Final)
97%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 97% — above average
97%
Career Allowance Rate
34 granted / 35 resolved
+29.1% vs TC avg
Minimal +4% lift
Without
With
+4.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
19 currently pending
Career history
57
Total Applications
across all art units

Statute-Specific Performance

§103
82.8%
+42.8% vs TC avg
§102
4.3%
-35.7% vs TC avg
§112
12.1%
-27.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 35 resolved cases

Office Action

§102 §103
Election/Restrictions Applicant’s election without traverse of Species 1 in the reply filed 04/06/2026 is acknowledged. Claims 1-20 remain pending. Claims 4-5 and 14-15 are withdrawn from consideration. Status of Claims Claims 1-20 are pending. Claims 4-5 and 14-15 are withdrawn from consideration. Claim Objections Claim 3 is objected to because of the following informalities: Claim 3 has incorrect punctuation in line 2 of the claim, specifically a comma and a period next to each other. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 8-9, 11-13, and 18-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0377905 A1 Kuo et al (herein “Kuo”). Regarding Claim 1, Kuo discloses: A package structure (see cross section of alternative embodiments shown in Figs. 14 and 19, along with specific manufacturing steps shown in Figs. 2-14, reference made to the embodiment shown in Fig. 19 unless otherwise specified), comprising: a substrate (#102, Fig. 2, [0021]); a first stack structure (#50, [0012]) located on the substrate and including at least one first chip ([0012]); a molding layer (#130) located on the substrate and encapsulating the first stack structure; and a first support structure (#116/116D, [0024]) penetrating through the molding layer and located on periphery (located on opposite sides of die) of the first stack structure, wherein the first support structure has a height (die not including overlying dielectric layers and connection pads has a smaller height than dummy through vias) greater than that of the first stack structure. Regarding Claim 2, Kuo discloses: The package structure of claim 1, wherein: the first support structure (#116/116D) is located on two opposite sides (left/right support structures shown in Fig. 19) of the first stack structure in a first direction (left/right direction in Figs. 17 and 19) parallel to a plane in which the substrate is located (see also [0073]-[0080] and top down view in Fig. 17). Regarding Claim 3, Kuo discloses: The package structure of claim 2, wherein, the first support structure has a size in a second direction (in/out direction in Fig. 19, up/down direction in Fig. 17) smaller than or equal to that of the molding layer (#130) in the second direction., wherein the second direction intersects the first direction (see Fig. 17). Regarding Claim 8, Kuo discloses: The package structure of claim 1, wherein the package structure includes a redundancy region and a wiring region, and wherein, the first support structure is located in at least one of the redundancy region or the wiring region (see annotated Fig. 17 below, wiring region corresponds to region adjacent to active portion of device, redundancy region corresponds to corner portion of device, see [0084]and [0085] of specification of instant application). PNG media_image1.png 827 794 media_image1.png Greyscale Fig. 17 – Annotated by Examiner Regarding Claim 9, Kuo discloses: The package structure of claim 1, wherein the first support structure has a mechanical strength greater than that of the molding layer ([0073]). Regarding Claim 11, Kuo discloses: A fabrication method of a package structure (see cross section of alternative embodiments shown in Figs. 14 and 19, along with specific manufacturing steps shown in Figs. 2-14, reference made to the embodiment shown in Fig. 19 unless otherwise specified), comprising: providing a substrate (#102, Fig. 2, [0021]); forming a first stack structure (#50, [0012]) on the substrate that comprises at least one first chip ([0012]); forming a molding layer (#130) encapsulating the first stack structure on the substrate; and forming a first support structure (#116/116D, [0024]) wherein the first support structure penetrates through the molding layer and is located on periphery (located on opposite sides of die) of the first stack structure, and the first support structure has a height (die not including overlying dielectric layers and connection pads has a smaller height than dummy through vias) greater than that of the first stack structure. Regarding Claim 12, Kuo discloses: The fabrication method of claim 11, wherein: the forming first support structure (#116/116D) comprises: forming the first support structure on two opposite sides (left/right support structures shown in Fig. 19) of the first stack structure in a first direction (left/right direction in Figs. 17 and 19) parallel to a plane in which the substrate is located (see also [0073]-[0080] and top down view in Fig. 17). Regarding Claim 13, Kuo discloses: The fabrication method of claim 12, wherein: the first support structure is formed on two opposite sides of the first stack structure in the first direction (in/out direction in Fig. 19, up/down direction in Fig. 17) smaller than or equal to that of the molding layer (#130) in the second direction., wherein the second direction intersects the first direction (see Fig. 17). Regarding Claim 18, Kuo discloses: the fabrication method of claim 11, wherein the package structure comprises a redundancy region and a wiring region; the forming the first support structure comprises: forming the first support structure in at least one of the redundancy region or the wiring region (see annotated Fig. 17 below, wiring region corresponds to region adjacent to active portion of device, redundancy region corresponds to corner portion of device, see [0084]and [0085] of specification of instant application). PNG media_image1.png 827 794 media_image1.png Greyscale Fig. 17 – Annotated by Examiner Regarding Claim 19, Kuo discloses: The fabrication method of claim 11, wherein the first support structure has a mechanical strength greater than that of the molding layer ([0073]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 6-7 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0377905 A1 Kuo et al. Regarding Claim 6, Kuo discloses: The package structure of claim 1, wherein the first support structure comprises a plurality of first support pillars disposed around the periphery of the first stack structure (#116/116D, see Fig. 19); Kuo does not explicitly disclose: the package structure further comprises: a second stack structure located on the substrate and disposed side by side with the first stack structure, the second stack structure comprising at least one second chip; and a second support structure penetrating through the molding layer and comprising: a plurality of second support pillars disposed around periphery of the second stack structure, wherein the second support structure has a height greater than that of the second stack structure. MPEP 2144.04 (VI) (B) states a mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In this case, nothing on the record indicates that a new or unexpected result is produced, rather the expected result of further integration of multiple package structures onto one common substrate. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider including a second stack structure including a second (or plurality of) second chip(s) and second support structures to be integrated onto a common substrate to form a functional semiconductor package structure. Regarding Claim 7, Kuo discloses: The package structure of claim 6, Kuo does not explicitly disclose: wherein the plurality of first support pillars have a first density distribution on the periphery of the first stack structure, the plurality of second support pillars have a second density distribution on the periphery of the second stack structure, and wherein the first density distribution and the second density distribution are same or different. However, the density distribution of the deposited first support pillars #116/116D is an implied property of the deposited material, and under the duplication of parts, specifically in regards to the duplication of the support structures mentioned in the rejection of claim 6 above, the second support structures would also have a density distribution (second density distribution). Under the duplication previously disclosed, the second density distribution would be the same as the first density distribution. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider forming the package structure such that the first and second support structures have a respective density distribution, and that the density distributions would be the same under the duplication of parts previously disclosed. Additionally, the formation of the support pillars results in reducing the risk of the redistribution lines cracking, see [0024], as well as the suppression of thermal expansion in the device. Consistent with the statements above, the density distribution of the deposited support pillars is an implied property of the device in order to function, that impacts the risk of cracking redistribution lines and suppression of thermal expansion, which may be adjusted by a person of ordinary skill to meet the needs of the device. This is therefore a result effective variable that impacts the structure and properties of the device that may be adjusted by a person of ordinary skill in the art to meet the needs of the device, specifically in an instance where the density distribution of one support pillar may need to be different than another for structural purposes within the device in order to function. See MPEP 2144.05 (II) (B). Regarding Claim 16, Kuo discloses: The fabrication method of claim 11, wherein the forming first support structure comprises: forming a plurality of first support pillars disposed around the periphery of the first stack structure (#116/116D, see Fig. 19); Kuo does not explicitly disclose: the fabrication method further comprises: forming a second stack structure disposed side by side with the first stack structure on the substrate, the second stack structure comprising at least one second chip; and forming a second support structure, wherein the second support structure penetrates through the molding layer and comprises: a plurality of second support pillars disposed around periphery of the second stack structure, and the second support structure has a height greater than that of the second stack structure. MPEP 2144.04 (VI) (B) states a mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In this case, nothing on the record indicates that a new or unexpected result is produced, rather the expected result of further integration of multiple package structures onto one common substrate. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider including a second stack structure including a second (or plurality of) second chip(s) and second support structures to be integrated onto a common substrate to form a functional semiconductor package structure. Regarding Claim 17, Kuo discloses: The fabrication method of claim 16, Kuo does not explicitly disclose: wherein the plurality of first support pillars have a first density distribution on the periphery of the first stack structure, the plurality of second support pillars have a second density distribution on the periphery of the second stack structure, and wherein the first density distribution and the second density distribution are same or different. However, the density distribution of the deposited first support pillars #116/116D is an implied property of the deposited material, and under the duplication of parts, specifically in regards to the duplication of the support structures mentioned in the rejection of claim 6 above, the second support structures would also have a density distribution (second density distribution). Under the duplication previously disclosed, the second density distribution would be the same as the first density distribution. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider forming the package structure such that the first and second support structures have a respective density distribution, and that the density distributions would be the same under the duplication of parts previously disclosed. Additionally, the formation of the support pillars results in reducing the risk of the redistribution lines cracking, see [0024], as well as the suppression of thermal expansion in the device. Consistent with the statements above, the density distribution of the deposited support pillars is an implied property of the device in order to function, that impacts the risk of cracking redistribution lines and suppression of thermal expansion, which may be adjusted by a person of ordinary skill to meet the needs of the device. This is therefore a result effective variable that impacts the structure and properties of the device that may be adjusted by a person of ordinary skill in the art to meet the needs of the device, specifically in an instance where the density distribution of one support pillar may need to be different than another for structural purposes within the device in order to function. See MPEP 2144.05 (II) (B). Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0377905 A1 Kuo et al in view of US 2021/0028103 A1 Huang et al (herein “Huang”). Regarding Claim 10, Kuo discloses: The package structure of claim 1, wherein the first support structure comprises metal, and wherein the molding layer comprises epoxy molding material ([0029] and [0032]). Kuo does not explicitly disclose: wherein the first support structure comprises organic composite material, silicon-based material. However, in analogous art, Huang teaches: wherein the first support structure comprises organic composite material, silicon-based material ([0045]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Huang to the device disclosed by Kuo and form the support pillars using an organic compound or using a silicon based compound. Doing so would be a simple substitution of one known material for another previously known the art for use as a support pillar within a package device. Regarding Claim 20, Kuo discloses: The fabrication method of claim 11, wherein the first support structure comprises metal, and the molding layer comprises epoxy molding material ([0029] and [0032]). Kuo does not explicitly disclose: wherein the first support structure comprises organic composite material, silicon-based material. However, in analogous art, Huang teaches: wherein the first support structure comprises organic composite material, silicon-based material ([0045]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Huang to the device disclosed by Kuo and form the support pillars using an organic compound or using a silicon based compound. Doing so would be a simple substitution of one known material for another previously known the art for use as a support pillar within a package device. Citation of Unused Pertinent Prior Art US 2016/0307871 A1 US 2018/0261557 A1 US 2008/0079159 A1 US 9601471 B2 Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000. /ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Aug 24, 2023
Application Filed
May 15, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685060
METHODS OF SEPARATING SEMICONDUCTOR DIES
3y 10m to grant Granted Jul 14, 2026
Patent 12685098
MULTI-FUNCTION ETCHING SACRIFICIAL LAYERS TO PROTECT THREE-DIMENSIONAL DUMMY FINS IN SEMICONDUCTOR DEVICES
3y 6m to grant Granted Jul 14, 2026
Patent 12672333
BACKSIDE PLACEHOLDER DIELECTRIC FILL
2y 6m to grant Granted Jun 30, 2026
Patent 12660534
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
3y 9m to grant Granted Jun 16, 2026
Patent 12635532
OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT
3y 6m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
97%
Grant Probability
99%
With Interview (+4.0%)
3y 4m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 35 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month