Prosecution Insights
Last updated: July 17, 2026
Application No. 18/455,500

ENHANCED BODY TIED TO SOURCE LOW NOISE AMPLIFIER DEVICE

Non-Final OA §103
Filed
Aug 24, 2023
Examiner
HOANG, DZUNG T
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
2 (Non-Final)
33%
Grant Probability
At Risk
2-3
OA Rounds
0m
Est. Remaining
33%
With Interview

Examiner Intelligence

Grants only 33% of cases
33%
Career Allowance Rate
1 granted / 3 resolved
-34.7% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
19 currently pending
Career history
20
Total Applications
across all art units

Statute-Specific Performance

§103
100.0%
+60.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 3 resolved cases

Office Action

§103
DETAILED ACTION Status of Claims The amendment filed on March 23, 2026 is entered. Claims 1 and 11 are amended, claims 5 and 15 are canceled, and no new appended claims. Claims 1-4, 6-14, and 16-20 are examined herein. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6-14, 16-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shi (US 20200357886 A1) in view of Dockerty (US 20020096719 A1). Re: Independent Claim 1, Shi discloses (annotated Fig. 11 below) a radio frequency (RF) device (Shi: ¶ [0013] disclosing each transistor can be configured as a radio-frequency transistor and ¶ [0053] disclosing one or more of the disclosed transistors can be configured as RF building blocks), comprising: PNG media_image1.png 586 692 media_image1.png Greyscale a semiconductor-on-insulator (SOI) substrate having a first-type diffusion region (Shi: annotated Fig. 11 above, and ¶ [0035] disclosing a silicon-on-insulator transistor); a transistor (transistor 100) on the first-type diffusion region and comprising a source region, a drain region, a gate region between the source region and the drain region, and a body region (¶ [0080] disclosing transistor 100 on N+ implant region 114, a source region 120, drain region 122, a gate region 124 between the source and drain and a body between the gate 124 and an insulator layer such as a gate oxide layer); and and a second-type diffusion encroachment region in the source region (Shi: Fig. 11 and ¶ [0070] disclosing a second-type diffusion region (P+ implant region 111a); P+ implant region 111a can be formed on a first side of a gate 124, but not on the other side to overlap the gate region, P+ active region 118a can be construed as the second-type diffusion encroachment region in the source region to form a body terminal region. Shi further discloses in ¶¶ [0071-0071] that a body is coupled to region 118a and the source (S) and the body (B) can have a common potential so as to provide V.sub.SB=0 across the butted P+/N+ interface 123. Note that it is well known in the art to short the body to the source to yield the Vsb = 0). wherein the gate region comprises a poly gate extension (rectangular (c)x(e) in Fig. 11 above) on a side of the drain region, the poly gate extension having a boundary extending to an edge of the first-type (drain region). Shi is silent regarding a second-type diffusion region, comprising a gate overlap region partially overlapped by the gate region to define the body region and the encroachment region adjoining the gate overlap region to form a body terminal region. Dockerty discloses the silicon-on-insulator transistor comprising N+ source region 36, N+ drain region 38, gate region 31, and P+ diffusion regions 32c are formed across bottom edge 36y overlapping the gate region (see Dockerty: ¶ [0020]). In the below annotated Fig. 2 down below, PNG media_image2.png 709 834 media_image2.png Greyscale Examiner construes region 32c comprising an encroachment region (S region) overlapping the source region and the contiguous gate overlap region (G region) as well as the contiguous extension (E region) placed across N+ source region 36 as described in Dockerty: ¶ [0029-0030]). Dockerty discloses the P+ diffusion region 32c are electrically shorted to N+ source region 36 via a salicide (see Dockerty: ¶ [0029]). Note that region 32c comprising the construed gate overlap G region, and the encroachment S region to form the body terminal region shorted to the source via a salicide, which is a siliciation method well known in the art. Shi discloses a P+ active encroachment region 118a in the source region in Fig. 11 that is shorted to the source. Dockerty discloses P+ diffusion 32c that encompasses an end of the source region (encroachment region) and extends to the edge of the gate 31 and in contact with P-type body region 34 then shorted to the source via a salicide. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to extend the P+ active region 118a of Shi to the P+ diffusion region 32c to guarantee the overlapping between the P+ diffusion region and the polysilicon gate, for the purpose of lowering the source-to-body resistance of the wide devices (see Dockerty: ¶ [0030]). Re: Claim 2, Shi and Dockerty disclose all the limitations of claim 1 on which this claim depends. Shi further discloses the RF device of claim 1, in which a width of the second-type diffusion encroachment region in the source region is less than a width of the first-type diffusion region in the source region (Shi: Fig. 11 showing the width of 118a is smaller than the width of the N+ source region 120). Re: Claim 3, Shi and Dockerty disclose all the limitations of claim 1 on which this claim depends. Shi further discloses the RF device of claim 1, in which a dimension (d) indicates a width of the second-type diffusion encroachment region in the source region (Shi: Fig. 11 annotated dimension (d) of the construed encroachment region 118a). Re: Claim 4, Shi and Dockerty disclose all the limitations of claim 1 on which this claim depends. Dockerty further discloses the RF device of claim 1, in which the second-type diffusion region comprises a second-type diffusion extension region, and a dimension (b) indicates an extension of the second-type diffusion region on a side of the source region having a length greater than a length of the drain region and shorted to the source region by the silicidation layer (Dockerty: Fig. 2 annotated dimension (b) of the construed extension E region as part of the region 32c formed across the source region 36. Note that 32c formed across N+ source region in all directions, crossing bottom edge 36y to extend to the edge of poly gate 31 forming the gate overlap region, crossing the top edge 36x to extend the length of the P+ diffusion region, and crossing the front or back edge of the source region to extend the width (b) of the extension region in the P+ diffusion region. Thus, the length of the extension region E region is greater than the length of the source and drain regions). Re: Claim 6, Shi and Dockerty disclose all the limitations of claim 1 on which this claim depends. Shi further discloses the RF device of claim 1, in which the gate region comprises a first poly gate extension at a first end of the gate region in the first-type diffusion region, and a second poly gate extension at a second end of the gate region, opposite the first end of the gate region, in the first-type diffusion region (Shi: Fig. 11 and ¶ [0076, 0080] disclosing gate 240 is of a polysilicon material and a P+ implant region. Fig. 11 showing the extension of gate 240 into the N+ drain region 122 and the N+ source region each at both ends). Re: Claim 7, Shi and Dockerty disclose all the limitations of claim 1 on which this claim depends. Shi further discloses the RF device of claim 1, in which the first-type diffusion region comprises an N+ diffusion region (Shi: ¶ [0005] disclosing the first type active region is an N+ active region). Re: Claim 8, Shi and Dockerty disclose all the limitations of claim 1 on which this claim depends. Shi further discloses the RF device of claim 1, in which the second-type diffusion region comprises a P+ diffusion region (Shi: ¶ [0080] disclosing second-type diffusion region 118a is a P+ body). Re: Claim 9, Shi and Dockerty disclose all the limitations of claim 1 on which this claim depends. Shi further discloses the RF device of claim 1, in which the RF device comprises an RF low noise amplifier (LNA) device (Shi: Fig. 27 and ¶¶ [0106-0110] disclosing RF device 900 comprising one or more low-noise amplifiers) Re: Claim 10, Shi and Dockerty disclose all the limitations of claim 9 on which this claim depends. Shi further discloses the RF device of claim 9, in which the RF LNA device is integrated in a radio frequency (RF) front end module, the RF front end module incorporated in at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer (Shi: Fig. 27 and ¶¶ [0106-0110] disclosing RF device 900 comprising one or more low-noise amplifier incorporated in a wireless device such as a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc.) Re: Independent Claim 11, Shi discloses a method of constructing a radio frequency (RF) device (Shi: abstract disclosing the implementation of a transistor and ¶ [0013] disclosing each transistor can be configured as a radio-frequency transistor), comprising: implanting a first-type diffusion region in a semiconductor-on-insulator (SOI) substrate (Shi: ¶ [0004] discloses "… in some implementations, the present disclosure relates to a transistor that includes a source and a drain each implemented as a first type active region …" and ¶ [0013] disclosing the substrate can include a silicon-on-insulator substrate); forming a transistor including a source region and a drain region in the first-type diffusion region, a gate region between the source region and the drain region, and a body region (Shi: Fig. 11 and ¶ [0014] disclosing "… with each transistor including a source and a drain each implemented as a first type active region, and a gate implemented relative to the source and the drain such that application of a voltage to the gate results in formation of a conductive channel between the source and the drain"); forming a second-type diffusion encroachment region (Shi: Fig. 11 diffusion region 118a) in the source region (Shi: Fig. 11 and ¶ [0080] disclosing the P+ body 118a is implemented on the first side (e.g., the source side associated with the N+ active region 120), but not on the other side (e.g., the drain side associated with the N+ active region 122). Note that examiner construes P+ region 118a as the encroachment region in the source region. Shi further discloses the construed encroachment region 118a is shorted to the source (Shi: ¶¶ [0082, 0084] disclosing a body coupled to the P+ body 118a and Vsb = 0). wherein the gate region comprises a poly gate extension (rectangular (c)x(e) in Fig. 11 above) on a side of the drain region, the poly gate extension having a boundary extending to an edge of the first-type (drain region). Shi is silent regarding a second-type diffusion region, comprising a gate overlap region partially overlapped by the gate region to define the body region and the encroachment region adjoining the gate overlap region to form a body terminal region. Dockerty discloses the silicon-on-insulator transistor comprising N+ source region 36, N+ drain region 38, gate region 31, and P+ diffusion regions 32c are formed across bottom edge 36y overlapping the gate region (see Dockerty: ¶ [0020]). In the below annotated Fig. 2 down below, Shi is silent regarding forming a second-type diffusion region, comprising a gate overlap region partially overlapped by the gate region to define the body region and the encroachment region adjoining the gate overlap region to form a body terminal region, a silicidation layer shorts the body terminal region to the source region. Dockerty discloses the body-tied-to-source transistor formed on silicon-on-insulator substrate (see Dockerty: ¶ [0027]). Dockerty further discloses forming a second-type diffusion region, comprising a gate overlap region partially overlapped by the gate region to define the body region and the encroachment region adjoining the gate overlap region to form a body terminal region (Dockerty: Fig. 2 and ¶ [0029] disclosing P+ diffusion region is formed across edge 36y of the N+ source region to extend to the edge of the poly gate 31. ¶ [0030] disclosing additional diffusions similar to 32c can be placed across N+ source region 36. Examiner construes the P+ diffusion 32c comprising of the encroachment region (S region) contiguous with the gate overlap region (G region) and the extension region (E region) as annotated in Fig. 2 above); and a silicidation layer shorts the body terminal region to the source region (Dockerty: ¶ [0029] disclosing P+ diffusion region is shorted to source region via a salicide. Note that salicide is a well-known silicidation method in the art). Shi discloses forming an encroachment region (Shi: Fig. 11 P+ active region 118a) that is shorted to the source. Dockerty discloses P+ diffusion region encompassing the encroachment region, gate overlap region and the extension region as annotated in Fig. 2 and the P+ diffusion region is shorted to the source via a salicide (Dockery: ¶ [0029]), Dorkerty further discloses (¶ [0030]) the poly gate 31 is extended by extended gate 31c to connect the gate to the P type diffusion 32c. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to extend the P+ active region 118a of Shi to the P+ diffusion region 32c to guarantee the overlapping between the P+ diffusion region and the polysilicon gate, for the purpose of lowering the source-to-body resistance of the wide devices (see Dockerty: ¶ [0030]). Re: Claim 12, Shi and Dockerty disclose all the limitations of claim 11 on which this claim depends. Shi further discloses the method of claim 11, in which a width of the second-type diffusion encroachment region in the source region is less than a width of the first-type diffusion region in the source region (Shi: Fig. 11 the P+ region 118a takes up a portion of the source region and that portion is smaller than the width of the N+ source region 120.) Re: Claim 13, Shi and Dockerty disclose all the limitations of claim 11 on which this claim depends. Shi further discloses the method of claim 11, in which a dimension (d) indicates a width of the second-type diffusion encroachment region in the source region (Shi: Fig. 11 annotated the width (d) of the P+ region 118a). Re: Claim 14, Shi and Dockerty disclose all the limitations of claim 11 on which this claim depends. Dockerty further discloses the method of claim 11, in which the second-type diffusion region comprises a second-type diffusion extension region, and a dimension (b) indicates an extension of the second-type diffusion region on a side of the source region having a length greater than a length of the drain region and shorted to the source region by the silicidation layer (Dockerty: annotated Fig. 2 and ¶ [0029] disclosing the E region extended cross the source region (having dimension (b)) and has a length (L) greater than the drain region, the E region as part of the region 32c is shorted to source region via a salicide). Re: Claim 16, Shi and Dockerty disclose all the limitations of claim 11 on which this claim depends. Shi further discloses the method of claim 11, in which the gate region comprises a first poly gate extension at a first end of the gate region in the first-type diffusion region, and a second poly gate extension at a second end of the gate region, opposite the first end of the gate region, in the first-type diffusion region (Shi: annotated Fig. 11 up above showing the poly gate 124 extended at both ends of the gate region at side of the N+ drain region. Fig. 11 also shows the poly gate 124 extended at both ends of the gate at a side of the N+ source region). Re: Claim 17, Shi and Dockerty disclose all the limitations of claim 11 on which this claim depends. Shi further discloses the method of claim 11, in which the first-type diffusion region comprises an N+ diffusion region (Shi: ¶ [0005] disclosing the first type region is an N+ type). Re: Claim 18, Shi and Dockerty disclose all the limitations of claim 11 on which this claim depends. Shi further discloses the method of claim 11, in which the second-type diffusion region comprises a P+ diffusion region (Shi: ¶ [0005] disclosing second type region is a P+ type). Re: Claim 19, Shi and Dockerty disclose all the limitations of claim 11 on which this claim depends. Shi further discloses the method of claim 11, in which the RF device comprises an RF low noise amplifier (LNA) device (Shi: Fig. 27 and ¶¶ [0106-0110] disclosing RF device 900 comprising one or more low-noise amplifiers). Re: Claim 20, Shi and Dockerty disclose all the limitations of claim 19 on which this claim depends. Shi further discloses the method of claim 19, further comprising integrating the RF LNA device in a radio frequency (RF) front end module, the RF front end module incorporated in at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer (Shi: Fig. 27 and ¶¶ [0106-0110] disclosing RF device 900 comprising one or more low-noise amplifier incorporated in a wireless device such as a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc.) Response to Amendment Applicant’s arguments have been considered but are moot in view of the new grounds of rejection. 13. Prior art made of record and not relied upon are considered pertinent to current application disclosure. Chen (US 20120012931 A1) and Houston (US 20020105014 A1) disclosing a P-type body contact region disposed in the N-type source region and shorted to the source via a silicide. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DTH/Examiner, Art Unit 2898 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Show 1 earlier event
Jan 23, 2026
Non-Final Rejection mailed — §103
Mar 10, 2026
Applicant Interview (Telephonic)
Mar 10, 2026
Examiner Interview Summary
Mar 23, 2026
Response Filed
May 12, 2026
Final Rejection mailed — §103
Jun 23, 2026
Applicant Interview (Telephonic)
Jun 23, 2026
Examiner Interview Summary
Jun 29, 2026
Response after Non-Final Action

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Prosecution Projections

2-3
Expected OA Rounds
33%
Grant Probability
33%
With Interview (+0.0%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 3 resolved cases by this examiner. Grant probability derived from career allowance rate.

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