DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a controller configured to perform operations comprising: determining…and controlling” in claim 1
Because these claim limitation(s) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10-13, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Savandaiah et al. US 2023/0032146 (“Savandaiah”).
Savandaiah discloses:
1. A system comprising:
a first processing chamber configured to perform a first fabrication process on a wafer (e.g., Fig. 1 #160A, Fig. 7 #701);
a second processing chamber configured to perform a second fabrication process on the wafer (e.g., Fig. 1 #160B, Fig. 7 #706);
a transfer chamber coupled to the first processing chamber and the second processing chamber (e.g., Fig. 1 #161A, Fig. 7 #702), wherein the transfer chamber comprises a sensor configured to measure wafer bowing characteristics associated with a bow of the wafer after the first fabrication process is performed on the wafer and before the second fabrication process is performed on the wafer (e.g., Fig. 7 #703,704, [0039], [0041], [0049], [0051]: “wafer bow and/or warp”);
a controller (e.g., Fig. 1 #199) configured to perform operations comprising:
determining recipe parameters to reduce the bow of the wafer based at least in part on the wafer bowing characteristics (e.g., Fig. 7 #706, [0053]); and
controlling environmental conditions in the transfer chamber and/or causing the second processing chamber to perform the second fabrication process using the recipe parameters (e.g., Fig. 7 #706, [0053]: “if it is determined at activity 704 that an out of tolerance condition has occurred, the substrate having the out of tolerance condition may be processed a second time in the same or a different process chamber to deposit additional material or to remove portions of material when doing so would bring the material layer thickness into tolerance”).
10. A method to reduce the bow of a wafer, the method comprising:
receiving, from a sensor coupled to a transfer chamber, wafer bowing characteristics associated with a bow of the wafer, the wafer bowing characteristics measured by the sensor (e.g., Fig. 7 #703,704, [0039], [0041], [0049], [0051]: “wafer bow and/or warp”), the transfer chamber (e.g., Fig. 1 #161A) coupled to a first processing chamber (e.g., Fig. 1 #160A) and a second processing chamber (e.g., Fig. 1 #160B), the first processing chamber configured to perform a first fabrication process on the wafer (e.g., Fig. 7 #701), the second processing chamber configured to perform a second fabrication process on the wafer (e.g., Fig. 7 #706);
determining recipe parameters for reducing the bow of the wafer based at least in part on the wafer bowing characteristics (e.g., Fig. 7 #706, [0053]); and
causing the second processing chamber to perform the second fabrication process using the recipe parameters (e.g., Fig. 7 #706, [0053]: “if it is determined at activity 704 that an out of tolerance condition has occurred, the substrate having the out of tolerance condition may be processed a second time in the same or a different process chamber to deposit additional material or to remove portions of material when doing so would bring the material layer thickness into tolerance”).
11. The method of claim 10, wherein the wafer bowing characteristics are measured by the sensor (e.g., Fig. 7 #703,704, [0039], [0041], [0049], [0051]: “wafer bow and/or warp”) as the wafer moves through the transfer chamber (e.g., Fig. 1 #161A) between the first processing chamber (e.g., Fig. 1 #160A) configured to perform the first fabrication process and the second processing chamber (e.g., Fig. 1 #160B) configured to perform the second fabrication process.
12. The method of claim 10, wherein the wafer bowing characteristics include a type of bowing comprising convex, concave, and combination (e.g., [0039], [0041], [0049], [0051]: “wafer bow and/or warp”, wafer bowing is defined as being either a convex or concave curvature of the wafer).
13. The method of claim 10, wherein the wafer bowing characteristics include displacement of one or more points of the wafer in comparison to a plane or the sensor (e.g., [0039], [0041], [0049], [0051]: “wafer bow and/or warp”, wafer bowing is defined as being a displacement of one or more points of the wafer in comparison to a plane).
17. The method of claim 13, wherein determining recipe parameters for reducing the bow of the wafer is further based at least in part on a thickness of film to be deposited by the second fabrication process in the second processing chamber (e.g., Fig. 7 #706, [0053]: “if it is determined at activity 704 that an out of tolerance condition has occurred, the substrate having the out of tolerance condition may be processed a second time in the same or a different process chamber to deposit additional material or to remove portions of material when doing so would bring the material layer thickness into tolerance”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Savandaiah in view of Cheng et al. US 2013/0171336 (“Cheng”).
Savandaiah does not explicitly disclose the features of claims 2 and 6.
Cheng (in combination with Savandaiah) discloses:
2. The system of claim 1, wherein the second processing chamber includes a pedestal, the pedestal including an electrostatic chuck and one or more heating zones (e.g., Fig. 2, [0016] of Cheng).
6. The system of claim 2, wherein causing the second processing chamber to perform the second fabrication process includes:
setting a chucking voltage of the electrostatic chuck based at least in part on the recipe parameters (e.g., [0035], [0048] of Cheng); and
adjusting the chucking voltage of the electrostatic chuck based at least in part on an indication of film thickness deposited by the second fabrication process in the second processing chamber (e.g., [0041], [0049] of Cheng).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Savandaiah with Cheng since Cheng teaches that controlling voltages to different zones of an electrostatic chuck serves to compensate for wafer warpage in the zone (e.g., [0048] of Cheng), and thus pertains to the same problem that Savandaiah is trying to solve, i.e., the correction of wafer warping (e.g., [0049] of Savandaiah).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Savandaiah as modified by Cheng as applied to claim 2 above, and further in view of Wong et al. US 2022/0384221 (“Wong”).
Savandaiah does not explicitly disclose the features of claim 5.
Wong (in combination with Savandaiah and Cheng) discloses:
5. The system of claim 2, wherein the one or more heating zones includes at least one inner zone and at least one outer zone; wherein causing the second processing chamber to perform the second fabrication process includes causing the at least one inner heating zone and the at least one outer heating zone to heat to different temperatures to reduce the bow of the wafer, the different temperatures being based at least in part on the recipe parameters (e.g., [0075] of Wong).
8. The system of claim 1, wherein determining recipe parameters for reducing the bow of the wafer is further based at least in part on throughput requirements for the system (e.g., [0075], [0084], [0092] of Wong).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Savandaiah and Cheng with Wong since Wong teaches an efficient methodology for compensating for wafer warp/bow by controlling subsequent manufacturing processes (e.g., [0002], [0075]), and thus pertains to the same problem that Savandaiah is trying to solve, i.e., the correction of wafer warping (e.g., [0049] of Savandaiah).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Savandaiah in view of Wong et al. US 2022/0384221 (“Wong”).
Savandaiah does not explicitly disclose the features of claim 8.
Wong (in combination with Savandaiah) discloses:
8. The system of claim 1, wherein determining recipe parameters for reducing the bow of the wafer is further based at least in part on throughput requirements for the system (e.g., [0075], [0084], [0092] of Wong).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Savandaiah with Wong since Wong teaches an efficient methodology for compensating for wafer warp/bow by controlling subsequent manufacturing processes (e.g., [0002], [0075]), and thus pertains to the same problem that Savandaiah is trying to solve, i.e., the correction of wafer warping (e.g., [0049] of Savandaiah).
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Savandaiah in view of Porter et al. US 2023/0136819 (“Porter”).
Savandaiah does not explicitly disclose wherein causing the second processing chamber to perform the second fabrication process includes setting a radio-frequency power applied to the second processing chamber based at least in part on the recipe parameters, as recited in claim 7; wherein determining the recipe parameters to reduce the bow of the wafer comprises adjusting a spacing between the wafer and the shower head in the first or second processing chamber to dynamically adjust a deposition rate or deposition uniformity, as recited in claim 9.
Porter (in combination with Savandaiah) discloses:
7. The system of claim 1, wherein causing the second processing chamber to perform the second fabrication process includes setting a radio-frequency power applied to the second processing chamber based at least in part on the recipe parameters (e.g., [0041], [0071], [0084], [0086]).
9. The system of claim 1, wherein determining the recipe parameters to reduce the bow of the wafer comprises adjusting a spacing between the wafer and the shower head in the first or second processing chamber to dynamically adjust a deposition rate or deposition uniformity (e.g., [0070]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Savandaiah with Porter since Porter teaches, in the case of claim 7, that RF power can be applied to a processing chamber in order to control film deposition thickness for the purpose of correcting wafer bow/warping (e.g., [0004]-[0005] of Porter), which pertains to the same problem that Savandaiah is trying to solve, i.e., the correction of wafer warping via film deposition processing (e.g., [0049] of Savandaiah).
Likewise, in the case of claim 9, Porter teaches that the wafer pedestal can be raised or lowered with respect to the showerhead in order to modulate process pressure and reactant concentration for the purposes of correcting wafer bow/warp (e.g., [0070]-[0071]).
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Savandaiah in view of Arora et al. US 2022/0074869 (“Arora”).
Savandaiah does not explicitly disclose the features of claims 14-16.
Arora (in combination with Savandaiah) discloses:
14. The method of claim 13, wherein the one or more points are distributed along a line across a diameter of the wafer (e.g., Fig. 1 #110, [0057]).
15. The method of claim 13, wherein the one or more points are distributed along two intersecting lines across the wafer (e.g., Fig. 1 #112, [0057]).
16. The method of claim 13, wherein the one or more points are distributed along a circle at a radius from a center of the wafer (e.g., Fig. 1 #116, [0057]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Savandaiah with Arora since Arora teaches that different measurement schemes can be effectively used to measure or derive a wafer bow (e.g., [0057]).
Allowable Subject Matter
Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or fairly suggest “wherein the pedestal includes pins; and wherein causing the second processing chamber to perform the second fabrication process includes causing wafer to soak in the second processing chamber on the pins for a time length based at least in part on the recipe parameters,” as recited in claim 3, in combination with the remaining features and elements of the claimed invention.
Claim 4 depends from claim 3 and is allowable by virtue of this dependency.
Claims 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to teach or fairly suggest “controlling environmental conditions in the transfer chamber using the recipe parameters,” as recited in claim 18, in combination with the remaining features and elements of the claimed invention.
Claims 19 and 20 depend from claim 18 and are allowable by virtue of this dependency.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhu et al. US 2020/0227294 also anticipates independent claims 1 and 10 (e.g., Fig. 2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A JARRETT whose telephone number is (571)272-3742. The examiner can normally be reached M-F 9:00-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Lo can be reached at 571-272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN A JARRETT/Primary Examiner, Art Unit 2116
05/22/26
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