Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant’s election without traverse of Group I, Embodiment 1 (FIGS. 1A-1H), which corresponds to claims 1-12 in the reply filed on 12/17/2025 is acknowledged. Therefore, claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 9,419,033; hereinafter Hsu) in view of Liu et al. (US 9,379,072; hereinafter Liu).
Regarding claim 1, Hsu, in fig. 1, discloses an image sensor, comprising: a chip 110 having a sensing area 113; a cover 130 covering the chip 110; a first dam layer 122; and a second dam layer 121, wherein the first dam layer 122 and the second dam layer 121 are located between the chip 110 and the cover 130 and surround the sensing area 113, the second dam layer 121 is located between the first dam layer 122 and the chip 110.
Hsu discloses an image sensor as above but fails to discloses a width of the first dam layer is greater than a width of the second dam layer, and the first dam layer is extended to the sensing area by a distance.
However, Liu, fig. 1G, discloses an image sensor, comprising: a first dam layer 260; and a second dam layer 220, wherein the width of the first dam layer 260 is greater than a width of the second dam layer 220, and the first dam layer 260 is extended to the sensing area 250 by a distance. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a dam combination as taught by Liu for reducing the opening the image sensing window, because when the image sensing window is a large opening, the image sensing area of an image sensor chip is easily contaminated during dam formation processes.
Regarding claim 2, Hsu discloses wherein a light transmittance of at least one of the first dam layer 122 and the second dam layer 121 is less than or equal to 30% (col. 3, lines 20-23).
Regarding claim 3, Hsu discloses wherein a material of the first dam layer 122 is different from a material of the second dam layer 121 (fig. 1).
Regarding claim 4, Hsu discloses wherein the first dam layer 122 comprises a photosensitive material, and the second dam layer 121 does not comprise the photosensitive material (col. 3, lines 20-23).
Regarding claim 5, Hsu discloses wherein a water absorption of at least one of the first dam layer 122 and the second dam layer 121 is less than or equal to 1% (col. 3, lines 20-23).
Regarding claim 6, Hsu discloses wherein an outer sidewall of the cover 130, an outer sidewall of the first dam layer 122, an outer sidewall of the second dam layer 121 are aligned with an outer sidewall of the chip 110 (fig. 1).
Regarding claim 7, Hsu discloses wherein the chip 110 comprises a circuit structure 114/115 surrounding the sensing area 113, and there is a gap between the first dam layer 122 and a top surface of the circuit structure 114/115 (fig. 1).
Regarding claim 8, Hsu discloses wherein the second dam layer 121 is extended from the top surface of the circuit structure 114/115 to cover an outer sidewall of the circuit structure 114/115 (fig. 1).
Regarding claim 9, Liu discloses wherein a bottom surface of the second dam layer 220 is lower than a bottom surface of the circuit structure 460 (fig. 1G).
Regarding claim 10, Hsu discloses wherein the second dam layer 121 has a gradually changing size at an extending portion of the outer sidewall of the circuit structure (col. 3, lines 46-59).
Regarding claim 11, Hsu discloses wherein the chip 110 comprises a landing pad 114, and the landing pad 114, the first dam layer 122, and the second dam layer 121 are overlapped in an orthographic projection direction (fig. 1).
Regarding claim 12, Liu discloses wherein a thickness of the first dam layer 260 is greater than a thickness of the second dam layer 220 (fig. 1G).
Conclusion
3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818