DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-6 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KOCON (US 6188105).
Regarding claim 1, KOCON discloses a trench MOSFET device having a first current terminal, a second current terminal and a gate terminal, the trench MOSFET device comprising:
a trench gate structure (the gate structure formed by 204 and 205, see fig 29-31, para 9) formed in a trench (the trench in which 204 and 205 are formed, see fig 29-31) in a semiconductor layer of a first conductivity type (the n-type epi layer 102, see fig 29-31, para 4), the trench gate structure including a conductive gate layer (fig 29-31, 205, para 9) formed in the trench and isolated from the semiconductor layer by a gate dielectric layer (fig 29-31, 204, para 9), the conductive gate layer forming the gate terminal (205 is a gate electrode, see para 9);
a body region of a second conductivity type (fig 29-31, elements 103 and 210, para 9) in and at a first surface of the semiconductor layer adjacent the trench (103 is at a top surface of 102 near the trench, see fig 31);
a first doped region of the first conductivity type (n-type source region 201, see fig 29-31, para 9) formed in the body region and at the first surface of the semiconductor layer adjacent the trench (201 is in 103 and is on a top surface of 102 near the trench, see fig 29-31), the first doped region forming the first current terminal (201 is a source region, which can be used as a current terminal, see fig 29-31), wherein the semiconductor layer forms the second current terminal (103 and 210 form a body region, see fig 29-31, para 10) ; and
a first body contact doped region of the second conductivity type (the portion of p+ region 210 shown in fig 30, see fig 29-31, para 10) formed in a first portion of the body region (210 is in 103, see fig 30) and spaced apart from the first doped region (210 is spaced apart from 201, see fig 30) and spaced apart from the trench (210 is spaced apart from 204, see fig 30), the first body contact doped region being more heavily doped than the body region (210 is a p+ region and 103 is a p region, see fig 30),
wherein the trench MOSFET device comprises a first MOSFET section formed in the first portion of the body region (the section of the device of fig 29 along the cross-section A-A shown in fig 30 which includes the body region 103 and 210) and a second MOSFET section formed outside of the first portion of the body region (the section of the device of fig 29 along the cross-section B-B shown in fig 31 which includes the body region 102 and 211), and
wherein the first MOSFET section has a first body contact resistance indicative of a resistance of the electrical connection to the body region in the first portion of the body region (the resistance between the source metal 212 and the p+ body contact region 210, see fig 30, para 11-12), and of the second MOSFET section has a second body contact resistance indicative of a resistance of the electrical connection to the body region outside of the first portion (the resistance between the source metal 212 to the body region 103 and 211 passing through the n+ source region 201, see fig 31, para 12), the first body contact resistance being lower than the second body contact resistance as a result of the first body contact doped region providing a low resistance connection to the body region in the first portion (the body contact region 210 is directly in electrical contact with 212 in 30, and is not in 31, so the resistance in fig 31 will be higher).
Regarding claim 3, KOCON discloses the trench MOSFET device of claim 1, wherein
the length of the trench extends in a first direction (the into-the-plane direction in fig 29-31) in the semiconductor layer and a width of the trench extends in a second direction (the horizontal direction in fig 29-31),
the second direction being orthogonal to the first direction and in the same plane as the first surface of the semiconductor layer (the top surface of the semiconductor layer is in the plane defined by the into-the-plane direction and the horizontal direction, see fig 29),
the length of the trench being larger than the width (see fig 29), and
wherein the body region formed in the semiconductor layer adjacent the trench extends in the first direction (103 extends in the into-the-plane direction, see fig 29) and the first portion of the body region comprises a portion of the body region positioned in the first direction (the first portion of 103 has a position in the into-the-plane direction, see fig 29).
Regarding claim 4, KOCON discloses the trench MOSFET device of claim 1, wherein
the first MOSFET section and the second MOSFET section form MOS transistors that are connected in parallel (both the transistors shown in fig 29 and the portions in A-A and B-B are both connected between the source metal 212 and the drain metal not shown, see para 11, and thus are in parallel),
wherein
the first doped region forms the first current terminals of the first and second MOSFET sections (the source region 201 is present in both portions, see fig 29-31),
the semiconductor layer forms the second current terminals of the first and second MOSFET sections (101 forms the drain region in both sections, see fig 29-31), and
the conductive gate layer forms the gate terminals of the first and second MOSFET sections (205 is formed in both regions, see fig 29-31).
Regarding claim 5, KOCON discloses the trench MOSFET device of claim 1, wherein
the first MOSFET section has a first transistor area and the second MOSFET section has a second transistor area, the first transistor area being a fraction of the second transistor area (the area around A-A being the first area can be defined such that it is smaller than the area around B-B being the second area, see fig 29-31).
Regarding claim 6, KOCON discloses the trench MOSFET device of claim 5, wherein the first transistor area is between 5% to 25% of the second transistor area (the area around A-A being the first area can be defined such that it is 5%-25% of the area around B-B being the second area, see fig 29-31).
Regarding claim 8, KOCON discloses the trench MOSFET device of claim 1, wherein
the trench MOSFET device comprises an array of trench transistor cells (the array of transistors shown in fig 29 include 103 and 201) defined by trench gate structures and associated body regions and first doped regions formed in the semiconductor layer between adjacent pair of trench gate structures (201 are formed between the trench gates 204/205, see fig 29),
the first MOSFET section including trench transistor cells formed in the first portion of the body regions including the first body contact doped region (the devices in the first portion on A-A include the p+ body contact region 210, see fig 30, para 11), and the second MOSFET section including trench transistor cells formed outside of the first portion of the body regions (the second region is outside A-A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 9-13 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOCON (US 6188105) in view of NAKAGAWA (US 20200243641).
Regarding claim 2, KOCON discloses the trench MOSFET device of claim 1, further comprising:
a conductive body contact (contact 212, see fig 29-31, para 11) formed in an isolation layer (ILD 207, see fig 29-31, para 9-10) formed over the semiconductor layer, the conductive body contact contacting the first doped region at the first surface of the semiconductor layer in areas of the body region outside of the first portion (212 directly contacts 201 in fig 31); and
the conductive body contact extending through the first doped region to be in contact with the first doped region and the first body contact doped region formed in the first portion of the body region (in fig 30, 212 extends through 201 to reach 210, see fig 30); and
wherein the first MOSFET section includes the conductive body contact making electrical contact with the first doped region and the first body contact doped region (212 is in direct contact with 201 and 210 in the first region as fig 30), and the second MOSFET section includes the conductive body contact making electrical contact only with the first doped region (212 makes direct electrical contact with 201 only in fig 31).
KOCON fails to explicitly disclose a device comprising a conductive layer formed above the isolation layer and in contact with the conductive body contact.
NAKAGAWA teaches a device comprising a conductive layer (502 is formed in contact with body contact layer 501, see fig 54, para 1204) formed above the isolation layer and in contact with the conductive body contact.
KOCON and NAKAGAWA are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOCON with the additional contact layer of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOCON with the additional contact layer of NAKAGAWA in order to improve withstand capacity and reduce feedback capacity (see NAKAGAWA para 339).
Regarding claim 9, KOCON discloses the trench MOSFET device of claim 1.
KOCON fails to explicitly disclose a device, further comprising:
a second body contact doped region of the second conductivity type formed in the body region outside of the first portion,
the second body contact doped region being spaced apart from the first doped region and spaced apart from the trench,
the second body contact doped region being more heavily doped than the body region and more lightly doped than the first body contact doped region.
NAKAGAWA teaches a device, further comprising:
a second body contact doped region of the second conductivity type formed in the body region outside of the first portion (fig 52, 455, para 1094),
the second body contact doped region being spaced apart from the first doped region and spaced apart from the trench (455 is spaced apart from 453 and 431, see fig 52),
the second body contact doped region being more heavily doped than the body region and more lightly doped than the first body contact doped region (455 can be more heavily doped that 426 and more lightly doped than 454, see para 1093-1094).
KOCON and NAKAGAWA are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOCON with the second body contact region of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOCON with the second body contact region of NAKAGAWA in order to improve withstand capacity and reduce feedback capacity (see NAKAGAWA para 339).
Regarding claim 10, KOCON and NAKAGAWA disclose the trench MOSFET device of claim 9.
KOCON fails to explicitly disclose a device, further comprising:
a conductive body contact formed in an isolation layer formed over the semiconductor layer, the conductive body contact extending through the first doped region to be in contact with the first doped region and the first body contact doped region formed in the first portion of the body region and the conductive .body contact extending through the first doped region to be in contact with the first doped region and the second body contact doped region formed in the body region outside of the first portion; and
a conductive layer formed above the isolation layer and in contact with the body contact,
wherein the first MOSFET section includes the conductive body contact contacting the first doped region and the first body contact doped region, and the second MOSFET section includes the conductive body contact contacting the first doped region and the second body contact doped region.
NAKAGAWA teaches a device, further comprising:
a conductive body contact (501 is in electrical contact with 426, see fig 54, para 1204) formed in an isolation layer formed over the semiconductor layer (501 is between portions of 491, see fig 54, para 994), the conductive body contact extending through the first doped region to be in contact with the first doped region and the first body contact doped region formed in the first portion of the body region (501 extends between portions of 453 to contact 453 and 454c, see fig 54, para 1205) and the conductive .body contact extending through the first doped region to be in contact with the first doped region and the second body contact doped region formed in the body region outside of the first portion (501 extends between portions of 453 to at least indirectly contact 453 and 455, see fig 54, para 1205); and
a conductive layer formed above the isolation layer and in contact with the body contact (502 extends above 491 and is in contact with 501, see fig 54, para 1206),
wherein the first MOSFET section includes the conductive body contact contacting the first doped region and the first body contact doped region (501 is at least indirectly in contact with 453 and 454c in LIV, see fig 52 and 54), and the second MOSFET section includes the conductive body contact contacting the first doped region and the second body contact doped region (501 is at least indirectly in contact with 453 and 455 outside LIV, see fig 52 and 54).
KOCON and NAKAGAWA are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOCON with the second body contact region of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOCON with the second body contact region of NAKAGAWA in order to improve withstand capacity and reduce feedback capacity (see NAKAGAWA para 339).
Regarding claim 11, KOCON and NAKAGAWA disclose the trench MOSFET device of claim 9.
KOCON further discloses a device, wherein
the length of the trench extends in a first direction (the into-the-plane direction in fig 29-31) in the semiconductor layer and a width of the trench extends in a second direction (the horizontal direction in fig 29-31), the second direction being orthogonal to the first direction and in the same plane as the first surface of the semiconductor layer, the length of the trench being larger than the width (the top surface of the semiconductor layer is in the plane defined by the into-the-plane direction and the horizontal direction, see fig 29), and
wherein the body region formed in the semiconductor layer adjacent the trench extends in the first direction (103 extends in the into-the-plane direction, see fig 29) and the first portion of the body region comprises a portion of the body region positioned in the first direction (the first portion of 103 has a position in the into-the-plane direction, see fig 29).
Regarding claim 12, KOCON and NAKAGAWA disclose the trench MOSFET device of claim 9.
KOCON further discloses a device, wherein
the first MOSFET section has a first transistor area and the second MOSFET section has a second transistor area, the first transistor area being a fraction of the second transistor area (the area around A-A being the first area can be defined such that it is smaller than the area around B-B being the second area, see fig 29-31).
Regarding claim 13, KOCON and NAKAGAWA disclose the trench MOSFET device of claim 12.
KOCON further discloses a device, wherein the first transistor area is between 5% to 25% of the second transistor area (the area around A-A being the first area can be defined such that it is 5%-25% of the area around B-B being the second area, see fig 29-31).
Regarding claim 15, KOCON and NAKAGAWA disclose the trench MOSFET device of claim 9.
KOCON further discloses a device, wherein
the trench MOSFET device comprises an array of trench transistor cells defined by trench gate structures and associated body regions and first doped regions formed in the semiconductor layer between adjacent pair of trench gate structures (the device of fig 29 comprises an array of transistor cells each of which has a gate 204/205, a source 201 and a body 103, see fig 29),
the first MOSFET section including trench transistor cells formed in the first portion of the body regions including the first body contact doped region (the devices formed in the region around A-A include the body contact region 210, see fig 29-31), and
the second MOSFET section including trench transistor cells formed outside of the first portion of the body regions (the second region around B-B is in a different part of the device than A-A, see fig 29-31).
Regarding claim 16, KOCON discloses a method for forming a trench MOSFET device, comprising:
providing a semiconductor layer of a first conductivity type (n-type epi layer 102, see fig 1, para 4);
forming an array of trench transistor cells in the semiconductor layer (the array of trench transistors shown in fig 29-31),
comprising
forming the trench transistor cells being defined by trench gate structures (the transistors have trench gates including 204 and 205, see fig 29-31, para 9);
forming body regions of a second conductivity type in the array of trench transistor cells (p-type body regions 103, 210 and 211 are formed, see fig 29-31, para 9);
forming source regions of the first conductivity type in the body regions of the array of trench transistor cells (source regions 201 are formed in 103, see fig 29-31);
forming a first body contact doped region of the second conductivity type in each body region in a first portion of the array of trench transistor cells (the body contact doped region 210 is formed in a portion of the device in fig 29 along the cross-section A-A as shown in fig 30, see para 10), the first body contact doped region being spaced apart from the source region formed in the respective body region (210 is spaced apart from 201, see fig 30) and spaced apart from the trench gate structure (210 is spaced apart from 205, see fig 30), the first body contact doped region being more heavily doped than the body region (210 is a p+ region and 103 is a p region, see fig 30, para 9-10);
forming a body contact (the metal layer 212, see fig 29-31, para 11) to make electrical contact with the source region and the first body contact doped region in each body region in the first portion of the array of trench transistors cells (212 is in direct contact with 201 and 210 in fig 30) and forming the body contact to make direct electrical contact only with the source regions in the body regions outside of the first portion of the array of trench transistors cells (in fig 31, which is along the cross-section B-B outside the region A-A is in, 212 is in direct electrical contact only with source 201, see fig 31, para 9).
KOCON fails to explicitly disclose a method comprising forming a first conductive layer in contact with the body contact.
NAKAGAWA teaches a method comprising forming a first conductive layer (502 is formed in contact with body contact layer 501, see fig 54, para 1204) in contact with the body contact.
KOCON and NAKAGAWA are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOCON with the second source conductor layer of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOCON with the second source conductor layer of NAKAGAWA in order to improve withstand capacity and reduce feedback capacity (see NAKAGAWA para 339).
Regarding claim 17, KOCON and NAKAGAWA disclose the method of claim 16.
KOCON further discloses a method, wherein forming the trench transistor cells being defined by trench gate structures comprises:
forming a conductive gate layer (fig 29-31, 205, para 9) in trenches formed in the semiconductor layer (205 is in trenches in 102, see fig 29), the conductive gate layer being isolated from the semiconductor layer by a gate dielectric layer (fig 29-31, 204, para 9) in each trench.
Regarding claim 18, KOCON and NAKAGAWA disclose the method of claim 16.
KOCON further discloses a method, wherein
a first MOSFET section is formed in the first portion of the array of trench transistor cells (the first portion shown in fig 30 is formed in the portion of the device of fig 30 around the cross-section A-A) and a second MOSFET section is formed outside of the first portion (the second portion shown in fig 31 is formed in the portion of the device of fig 29 around the cross-section B-B which is a different part of the device),
the first MOSFET section having a body contact resistance lower than a body contact resistance of the second MOSFET section (the body contact region 210 is directly in electrical contact with 212 in 30, and is not in 31, so the resistance in fig 31 will be higher).
Regarding claim 19, KOCON and NAKAGAWA disclose the method of claim 16.
KOCON further discloses a method, wherein the first MOSFET section has a first transistor area and the second MOSFET section has a second transistor area, the first transistor area being a fraction of the second transistor area (the area around A-A being the first area can be defined such that it is smaller than the area around B-B being the second area, see fig 29-31).
Regarding claim 20, KOCON and NAKAGAWA disclosed method of claim 16.
KOCON fails to explicitly disclose a method, further comprising:
forming a second body contact doped region of the second conductivity type in each body region outside of the first portion, the second body contact doped region being spaced apart from the source region formed in the respective body region and spaced apart from the trench gate structure, the second body contact doped region being more heavily doped than the body region and more lightly doped than the first body contact doped region; and
forming the body contact to the first body contact doped region in the first portion of the trench transistor cells and to the second body contact doped region outside of the first portion.
NAKAGAWA teaches a method, further comprising:
forming a second body contact doped region of the second conductivity type (fig 54, 455, para 1089) in each body region outside of the first portion, the second body contact doped region being spaced apart from the source region formed in the respective body region and spaced apart from the trench gate structure (455 is spaced apart from source 453 and gate 434, see fig 54), the second body contact doped region being more heavily doped than the body region and more lightly doped than the first body contact doped region (455 can be more heavily doped than 426, see para 1093, and 455 can be less heavily doped than 454, see para 1094); and
forming the body contact to the first body contact doped region in the first portion of the trench transistor cells and to the second body contact doped region outside of the first portion (501 is at least indirectly in contact with 455, see fig 54).
KOCON and NAKAGAWA are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOCON with the second body contact region of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOCON with the second body contact region of NAKAGAWA in order to improve withstand capacity and reduce feedback capacity (see NAKAGAWA para 339).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOCON (US 6188105) in view of NISHIWAKI (US 20190288071).
Regarding claim 7, KOCON discloses the trench MOSFET device of claim 1.
KOCON fails to explicitly disclose a device, wherein
the first MOSFET section has a first threshold voltage and the second MOSFET section has a second threshold voltage,
the first threshold voltage being greater than the second threshold voltage.
NISHIWAKI teaches a device, wherein
the first MOSFET section has a first threshold voltage (each transistor cell has a threshold voltage Vth2, see fig 2-3, para 64) and the second MOSFET section has a second threshold voltage (each transistor cell has another threshold voltage Vth1, see fig 2-3, para 64),
the first threshold voltage being greater than the second threshold voltage (Vth2>Vth1, see para 64).
KOCON and NISHIWAKI are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOCON with the different threshold voltages of NISHIWAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOCON with the different threshold voltages of NISHIWAKI in order to make moderate the rise-up of the drain current (see NISHIWAKI para 71).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOCON (US 6188105) in view of NAKAGAWA (US 20200243641) and further in view of NISHIWAKI (US 20190288071).
Regarding claim 14, KOCON and NAKAGAWA disclose the trench MOSFET device of claim 9.
KOCON fails to explicitly disclose a device, wherein
the first MOSFET section has a first threshold voltage and the second MOSFET section has a second threshold voltage,
the first threshold voltage being greater than the second threshold voltage.
NISHIWAKI teaches a device, wherein
the first MOSFET section has a first threshold voltage (each transistor cell has a threshold voltage Vth2, see fig 2-3, para 64) and the second MOSFET section has a second threshold voltage (each transistor cell has another threshold voltage Vth1, see fig 2-3, para 64),
the first threshold voltage being greater than the second threshold voltage (Vth2>Vth1, see para 64).
KOCON and NISHIWAKI are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOCON with the different threshold voltages of NISHIWAKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOCON with the different threshold voltages of NISHIWAKI in order to make moderate the rise-up of the drain current (see NISHIWAKI para 71).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 16 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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