DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed November 19, 2025.
Claims 1-22 are pending. Claims 1, 3-5, 9, 11, 13-15 and 19 are amended. Claims 1, 11 and 19 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on September 21, 2023.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10-14 and 17-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2020/0133574; hereinafter “Lee”) in view of Lo (U.S. 2017/0293437).
Regarding independent claim 1, Lee teaches a memory device (Fig. 1) comprising:
a memory cell array (Fig. 6) including a plurality of memory cells (Fig. 6: MCs) which are coupled between a plurality of word lines (Fig. 6: WLs) and a plurality of bit lines (Fig. 6: BLs); and
a control circuit (Fig. 1: 126-127 and 200) configured to:
select a search group through a group-based binary search method for a plurality of groups obtained by grouping the plurality of word lines by a set number in an entry period of a search mode (see page 13, par. 0205),
perform a checking operation of simultaneously checking whether a boundary word line exists among word lines of the search group and at which location among the word lines of the search group the boundary word line is located (see page 13, par. 0205-0213), on the basis of a search current glowing through the plurality of bit lines (see page 4, par. 0060), in a state in which a detection voltage is applied to all word lines of the search group each time the search group is selected (Fig. 12: Vread),
generate location information when a location of the boundary word line is checked in the checking operation (see page 13, par. 0213), and
exit the search mode after outputting the location information to the outside (Fig. 17: end; see also page 5, par. 0072).
However, Lee is silent with respect to perform a checking operation of simultaneously checking whether a boundary word line exists among word lines, on the basis of a comparison between a magnitude of a search current obtained by summing currents respectively flowing through the plurality of bit lines and a magnitude of a reference current.
Similar to Lee, Lo teaches a memory device (Fig. 2) comprising a memory cell array (Fig. 1: 10) including a plurality of memory cells (Fig. 1: cell) which are coupled between a plurality of word lines (Fig. 1: word lines) and a plurality of bit lines (Fig. 1: bit lines).
Furthermore, Lo teaches perform a checking operation of simultaneously checking whether a boundary word line exists among word lines (see page 3, par. 0052), on the basis of a comparison between a magnitude of a search current obtained by summing currents respectively flowing through the plurality of bit lines and a magnitude of a reference current (see page 6, par. 0073).
Since Lo and Lee are from the same field of endeavor, the teachings described by Lo would have been recognized in the pertinent art of Lee.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lo with the teachings of Lee for the purpose of efficiently reduce communication bandwidth between a controller and a flash memory, see Lo’s page 1, par. 0003.
Regarding claim 2, Lee in combination with Lo teaches the limitations with respect to claim 1.
Furthermore, Lee teaches wherein, during a period in which the detection voltage is applied simultaneously to all word lines of the search group (Fig. 12: Vread), the control circuit applies a pass voltage simultaneously to all word lines of remaining groups except the search group (Fig. 12: Vpass).
Regarding claim 3, Lee in combination with Lo teaches the limitations with respect to claim 1.
Furthermore, Lee teaches wherein the control circuit enters the search mode in response to a search command inputted from the outside (Fig. 3: last page read command), and selects an initial search group in response to select information inputted from the outside after the search command (Fig. 12: Group1), and
when it is checked, on the basis of the magnitude of the search current in the checking operation, that the boundary word line does not exist among the word lines of the search group, the control circuit performs the checking operation again by reselecting a search group (see page 13, par. 0210-0211).
Regarding claim 4, Lee in combination with Lo teaches the limitations with respect to claim 3.
Furthermore, Lee teaches wherein, when existence and a location of the boundary word line among the word lines of the search group are simultaneously checked on the basis of the magnitude of the search current in the checking operation (see page 13, par. 0205-0213), the control circuit generates the location information corresponding to the checked location and exits the search mode after outputting the location information to the outside (Fig. 3: last page data).
Regarding claim 10¸ Lee in combination with Lo teaches the limitations with respect to claim 1.
Furthermore, Lee teaches wherein the boundary word line is, among the plurality of word lines, a word line in an erase state which is adjacent to a word line in a program state or a word line in a program state which is adjacent to a word line in an erase state (see Fig. 10).
Regarding independent claim 11, Lee teaches a memory system (Fig. 1) comprising:
a controller (Fig. 1: 200) configured to generate and output a search command (Fig. 3: last page read command) when power is resumed after a sudden power-off (SPO), and perform a recovery operation in response to location information (see page 4, par. 0065-0066); and
a first memory device (Fig. 3: 100) including a plurality of memory cells (Fig. 6: MCs) which are coupled between a plurality of word lines (Fig. 6: WLs) and a plurality of bit lines (Fig. 6: BLs), and a control circuit configured to:
select a search group through a group-based binary search method for a plurality of groups obtained by grouping the plurality of word lines by a set number, in a state in which a search mode is entered in response to the search command mode (see page 13, par. 0205),
perform a checking operation of checking whether a boundary word line exists among word lines of the search group and at which location among the word lines of the search group the boundary word line is located (see page 13, par. 0205-0213), on the basis of a search current flowing through the plurality of bit lines (see page 4, par. 0060), in a state in which a detection voltage is applied to all word lines of the search group each time the search group is selected (Fig. 12: Vread),
generate location information when a location of the boundary word line is checked in the checking operation (see page 13, par. 0213), and
output the location information to the controller (Fig. 3: last page data).
However, Lee is silent with respect to perform a checking operation of checking whether a boundary word line exists among word lines, on the basis of a comparison between a magnitude of a search current obtained by summing currents respectively flowing through the plurality of bit lines and a magnitude of a reference current.
Similar to Lee, Lo teaches a first memory device (Fig. 2) including a plurality of memory cells (Fig. 1: cell) which are coupled between a plurality of word lines (Fig. 1: word lines) and a plurality of bit lines (Fig. 1: bit lines).
Furthermore, Lo teaches to perform a checking operation of checking whether a boundary word line exists among word lines (see page 3, par. 0052), on the basis of a comparison between a magnitude of a search current obtained by summing currents respectively flowing through the plurality of bit lines and a magnitude of a reference current (see page 6, par. 0073).
Since Lo and Lee are from the same field of endeavor, the teachings described by Lo would have been recognized in the pertinent art of Lee.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lo with the teachings of Lee for the purpose of efficiently reduce communication bandwidth between a controller and a flash memory, see Lo’s page 1, par. 0003.
Regarding claim 12, Lee in combination with Lo teaches the limitations with respect to claim 11.
Furthermore, Lee teaches wherein, during a period in which the detection voltage is applied simultaneously to all word lines of the search group (Fig. 12: Vread), the control circuit applies a pass voltage simultaneously to all word lines of remaining groups except the search group (Fig. 12: Vpass).
Regarding claim 13, Lee in combination with Lo teaches the limitations with respect to claim 11.
Furthermore, Lee teaches wherein the control circuit enters the search mode in response to the search command inputted from the outside (Fig. 3: last page read command), and selects an initial search group in response to select information inputted from the controller after the search command (Fig. 12: Group1), and
when it is checked, on the basis of the magnitude of the search current in the checking operation, that the boundary word line does not exist among the word lines of the search group, the control circuit performs the checking operation again by reselecting a search group (see page 13, par. 0210-0211).
Regarding claim 14, Lee in combination with Lo teaches the limitations with respect to claim 13.
Furthermore, Lee teaches wherein, when existence and a location of the boundary word line among the word lines of the search group are simultaneously checked on the basis of a magnitude of the search current in the checking operation (see page 13, par. 0205-0213), the control circuit generates the location information corresponding to the checked location and exits the search mode after outputting the location information to the controller (Fig. 3: last page data).
Regarding claim 17¸ Lee in combination with Lo teaches the limitations with respect to claim 11.
Furthermore, Lee teaches wherein the boundary word line is, among the plurality of word lines, a word line in an erase state which is adjacent to a word line in a program state or a word line in a program state which is adjacent to a word line in an erase state (see Fig. 10).
Regarding claim 18, Lee in combination with Lo teaches the limitations with respect to claim 11.
Furthermore, Lee teaches a second memory device configured to write or read data to or from a storage area therein under control of the controller, in a state in which the first memory device enters the search mode (Fig. 8: Spare Area, see also Abstract).
Regarding independent claim 19, Lee teaches a method for operating a memory device (Fig. 1) including a plurality of memory cells (Fig. 6: MCs) coupled between a plurality of word lines (Fig. 6: WLs) and a plurality of bit lines (Fig. 6: BLs), the method comprising:
entering a search mode in response to a search command (Fig. 3: last page read command);
selecting a search group through a group-based binary search method for a plurality of groups obtained by grouping the plurality of word lines by a set number in an entry period of the search mode (see page 13, par. 0205);
performing a checking operation of checking whether a boundary word line exists among word lines of the search group selected in the selecting and at which location among the word lines of the search group the boundary word line is located (see page 13, par. 0205-0213), on the basis of a search current flowing through the plurality of bit lines (see page 4, par. 0060), in a state in which a detection voltage is applied to all word lines of the search group (Fig. 12: Vread); and
repeating the selecting and the checking when the boundary word line does not exist among the word lines of the search group in the checking operation (see page 13, par. 0210-0211), generating location information when a location of the boundary word line is checked (see page 13, par. 0213), and exiting the search mode after outputting the location information to the outside (Fig. 17: end; see also page 5, par. 0072).
However, Lee is silent with respect to performing a checking operation of checking whether a boundary word line exists among word lines, on the basis of a comparison between a magnitude of a search current obtained by summing currents respectively flowing through the plurality of bit lines and a magnitude of a reference current.
Lo teaches performing a checking operation of checking whether a boundary word line exists among word lines (see page 3, par. 0052), on the basis of a comparison between a magnitude of a search current obtained by summing currents respectively flowing through the plurality of bit lines and a magnitude of a reference current (see page 6, par. 0073).
Since Lo and Lee are from the same field of endeavor, the teachings described by Lo would have been recognized in the pertinent art of Lee.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lo with the teachings of Lee for the purpose of efficiently reduce communication bandwidth between a controller and a flash memory, see Lo’s page 1, par. 0003.
Regarding claim 20, Lee in combination with Lo teaches the limitations with respect to claim 19.
Furthermore, Lee teaches wherein the checking includes applying, during a period in which the detection voltage is applied simultaneously to all word lines of the search group (Fig. 12: Vread), a pass voltage simultaneously to all word lines of remaining groups except the search group (Fig. 12: Vpass).
Regarding claim 21, Lee in combination with Lo teaches the limitations with respect to claim 19.
Furthermore, Lee teaches wherein the selecting comprises:
selecting an initial search group in response to select information inputted from the outside after the search command (Fig. 12: Group1); and
reselecting a search group according to the binary search method each time the operation control act is repeated (see page 13, par. 0210-0211).
Regarding claim 22¸ Lee in combination with Lo teaches the limitations with respect to claim 19.
Furthermore, Lee teaches wherein the boundary word line is, among the plurality of word lines, a word line in an erase state which is adjacent to a word line in a program state or a word line in a program state which is adjacent to a word line in an erase state (see Fig. 10).
Allowable Subject Matter
Claims 5-9 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 5, there is no teaching or suggestion in the prior art of record to provide the recited page buffer unit configured to output the search current by summing currents flowing through the plurality of bit lines, respectively; a current comparison unit coupled to the page buffer unit, and configured to compare the magnitude of the search current with the magnitude of the reference current in the entry period of the search mode and generate a detection code by varying a value thereof according to a comparison result; and a control logic unit configured to: select the search group as one of the plurality of groups in the entry period of the search mode, perform the checking operation on the basis of a value of the detection code generated in the current comparison unit after applying the detection voltage simultaneously to all word lines of the search group and applying the pass voltage simultaneously to all word lines of the remaining groups each time the search group is selected, generate the location information when a location of the boundary word line is checked in the checking operation, and exit the search mode after outputting the location information to the outside.
With respect to claim 15, there is no teaching or suggestion in the prior art of record to provide the recited page buffer unit configured to output the search current by summing currents flowing through the plurality of bit lines, respectively; a current comparison unit coupled to the page buffer unit, and configured to compare the magnitude of the search current with the magnitude of the reference current in an entry period of the search mode and generate a detection code by varying a value thereof according to a comparison result; and a control logic unit configured to: select the search group as one of the plurality of groups in the entry period of the search mode, perform the checking operation on the basis of a value of the detection code generated in the current comparison unit after applying the detection voltage simultaneously to all word lines of the search group and applying the pass voltage simultaneously to all word lines of the remaining groups each time the search group is selected, generate the location information when a location of the boundary word line is checked in the checking operation, and exit the search mode after outputting the location information to the controller.
Response to Arguments
Applicant’s arguments with respect to claims 1-4, 10-14 and 17-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825