Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 6, 12, 15, 18 and 20
b. Pending: 1-20
Claims 1, 3, 6-7, 9, 12 and 18-20 have been amended.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/22/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the precharge command" in line: 7. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-5 carry the same deficit due to dependency chain and henceforth are rejected.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claims 1, 6, 12, 15, 18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: relationship between signals. All the claim limitations cite that one signal is being generated “according” to another signal/command or so. But there is no clarity on how to generate the output signals. PHOSITA would not know the logical relationship between inputs and outputs.
Claims 2-5, 7-11, 13-14, 16-17 and 19 carry the same deficit due to dependency chain and henceforth are rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Fujino et al. (US 6507532).
Regarding independent claim 12, Fujino discloses an operating method of a memory device (Figs. 26-28), the operating method comprising:
generating an internal precharge signal according to an active command (Fig. 26A and (12) shows active command ACT generating an internal signal that is output from composite gate circuit 900);
activating at least one first word line corresponding to one of an active address and an adjacent address according to the active command ((13) describes generating word line activation signal RXT. Fig. 27 and (24) describes when active command ACT is supplied, latch circuit 910 latches address signal RA. (27) describes according to word line activation signal RXT, a word line corresponding to an addressed row can be driven into the selected state so that the selected word line is maintained in the selected state during the period in which the bank is activated), and deactivating the activated first word line according to the internal precharge signal (Fig. 26A and (12) describes that precharge command PRG instructing bank inactivation);
generating an internal active signal according to the internal precharge signal (Fig. 26A and (12) shows generating bank activation signal RASE based on output from unit 900); and
activating at least one second word line corresponding to the remaining one of the active address and the adjacent address according to the internal active signal, and deactivating the activated second word line according to a precharge command (here examiner asserts that the process of activation and inactivation is repetitive and this is an obvious design variation).
Regarding claim 13, Fujino discloses all the elements of claim 12 as above and further generating the active address by latching an input address according to the active command; and generating adjacent address candidates by adding or subtracting a certain value to or from the active address, and outputting one of the adjacent address candidates as the adjacent address (Figs. 27-28 and (22)-(27)).
Regarding independent claim 15, Fujino discloses an operating method of a memory device (Figs. 26-28), the operating method comprising:
activating at least one first word line corresponding to one of an active address and an adjacent address according to an active command ((13) describes generating word line activation signal RXT. Fig. 27 and (24) describes when active command ACT is supplied, latch circuit 910 latches address signal RA. (27) describes according to word line activation signal RXT, a word line corresponding to an addressed row can be driven into the selected state so that the selected word line is maintained in the selected state during the period in which the bank is activated), and deactivating the activated first word line according to a precharge command (Fig. 26A and (12) describes that precharge command PRG instructing bank inactivation);
generating an internal active signal according to the precharge command (Figs. 8A-8B output from composite gate 20c is generated based on precharge command PRG);
generating an internal precharge signal according to the internal active signal (Figs. 8A-8B and (47) describes bank activation signal RASE being generated based on output from composite gate 20c); and
activating at least one second word line corresponding to the remaining one of the active address and the adjacent address according to the internal active signal, and deactivating the activated second word line according to the internal precharge signal (here examiner asserts that the process of activation and inactivation is repetitive and this is an obvious design variation).
Regarding claim 16, Fujino discloses all the elements of claim 16 as above and further generating the active address by latching an input address according to the active command; and generating adjacent address candidates by adding or subtracting a certain value to or from the active address, and outputting one of the adjacent address candidates as the adjacent address (Figs. 27-28 and (22)-(27)).
Claims 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Fujino et al. (US 6507532) in view of Ha (US 7161858).
Regarding claim 14, Fujino discloses all the elements of claim 12 as above and through Ha further the internal precharge signal is activated after a minimum row active time (tRASmin) from an input of the active command (Figs. 3, 5A-5B and claim 1 all describes tRASmin), and wherein the internal active signal is activated after a minimum precharge time (tRPmin) from an activation of the internal precharge signal (here examiner asserts that these signals are repetitive in nature and one comes after the other with certain delays).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Ha to modified Fujino in order to provide with a semiconductor memory device including an active driving block for generating an internal active signal to drive a bank, a precharge signal generating block for producing an internal precharge signal to precharge the bank, and an active drive securing block for controlling the precharge signal generating block to make the internal precharge signal actuated after a minimum row active time is passed in response to the internal active signal as taught by Ha ((22)).
Claim 17 recites the same claim limitations of claim 14 and henceforth rejected the same way.
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 2/18/2026