Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species I, claims 1-3 and 6-8 in the reply filed on February 6, 2026 is acknowledged.
Claims 4 and 5 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claims 1-3 and 6-8 are examined below.
Specification
The abstract of the disclosure is objected to because it exceeds 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The specification is objected to for minor informalities: Paragraph [0012] of the specification states that figure 2 illustrates a portion of the y-z cross-section of the memory cell array, while figure 2 actually illustrates the x-z cross-section.
Claim Objections
Claim 1 is objected to because of the following informalities: “a second insulating film that disposed between the second wiring and the second oxide” needs grammatical correction.
Claims 7 and 8 are objected to because of the following informalities: includes should be include because the subject of these sentences (first layer and second layer) is plural.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6, 7 and 8 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Atanasov US 20220189957 A1.
Regarding claim 1, Atanasov discloses a semiconductor storage device comprising:
a first oxide semiconductor layer extending in a first direction (Element 120 of figure 1 is an oxide semiconductor material layer [0020], extending (vertically in figure 1) in a first direction, z);
a second oxide semiconductor layer extending in the first direction and being adjacent to the first oxide semiconductor layer in a second direction intersecting the first direction (Figure 12 discloses the arrangement (viewed in the x-y plane) of the plurality of transistors that include a plurality of oxide semiconductor layers [0025]. Therefore, there is a second oxide layer extending in the z direction (In figure 12, the z direction is perpendicular to the plane of the figure) and adjacent to the first oxide semiconductor layer in the x direction (In figure 12, x is the vertical direction)).
first wiring (figure 1, “first memory control lines” 126, [0024]) extending in a third direction (the y direction, which in figure 1 extends left to right) intersecting the first direction and overlapping the first oxide semiconductor layer (figure 1, 120) in the third direction (Figure 1 illustrates that memory control line 126 lies to the right and left of oxide semiconductor layer 120, thus overlapping layer 120 in the y direction.);
second wiring extending in the third direction and overlapping the second oxide semiconductor layer in the third direction (see the rejection of the last limitation, as there is a corresponding second wiring for the second oxide layer in the arrangement of memory cells in figure 12);
a first insulating film (gate dielectric layer 122 in figure 1) disposed between the first wiring (figure 1, 126) and the first oxide semiconductor layer (120);
a second insulating film that disposed between the second wiring and the second oxide semiconductor layer (see the rejection of the last limitation, as there is a corresponding insulating film in the arrangement of memory cells in figure 12);
a first conductor (figure 1, gate electrode 124, [0017]) disposed on the first oxide semiconductor layer (120);
a second conductor disposed on the second oxide semiconductor layer (see the rejection of the last limitation, as there is a corresponding conductor in the arrangement of memory cells in figure 12);
an insulating layer having a gap between the first conductor and the second conductor or between the first wiring and the second wiring (The insulating layer (figure 1, 116) has, between the two conductors (first conductor is 124 in figure 1, and the second conductor is the corresponding 124 in the direction out of the plane of figure 1), at least one gap (liner layers 118 in figure 1, which create spaces in layer 116 as described in paragraph [0016]). Because having the gap “between the first wiring and the second wiring ‘is part of an alternative 'or' limitation, this is not required by the prior art to read on the claim as presented).
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Regarding claim 3, Atanasov discloses the semiconductor storage device according to claim 1, further comprising: an insulating film disposed between each of the first wiring, the second wiring, the first conductor, and the second conductor, and the gap. The insulating film layer 116 is disposed between all combinations of these elements, as indicated by the double-headed arrows in the annotated figures above: For the five elements – 1st wiring (A), 2nd wiring (B), 1st conductor (C), 2nd conductor (D), and the gap (E), there are 10 unique pairs of these elements, four of which pairs are essentially duplicates due to the symmetry between the 1st and 2nd conductors and 1st and 2nd wirings. As indicated by the arrows in the annotated figure, lines connecting each of the remaining 6 element pairs extend from the first element of the pair and cross the insulating layer 116 before reaching the second element of the pair; therefore, the layer 116 is located between all these elements.
Regarding claim 6, Atanasov discloses the semiconductor storage device according to claim 1, wherein the semiconductor storage device includes a memory cell array (described in paragraphs [0001], [0010], and [0032]).
Regarding claim 7, Atanasov discloses the semiconductor storage device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer includes indium, gallium and zinc (the oxide semiconductor layers may include indium gallium zinc oxide (IGZO) [0020]).
Regarding claim 8, Atanasov discloses the semiconductor storage device according to claim 1, wherein the first insulating film (122) and the second insulating film (122) include silicon and at least one of nitrogen or oxygen: the insulating film 122 is a high-k dielectric and may comprise hafnium silicon oxide, zirconium silicon oxide, or tantalum silicon oxide [0022], all of which include silicon and oxygen.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Atanasov in view of Chien et al. US 20200335506 A1.
Regarding claim 2, Atanasov discloses the semiconductor storage device according to claim 1, further comprising:
a third conductor disposed between the first conductor and the second conductor: annotations of figure 12 indicate the positions of first, second, and third
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conductors, where the third conductor (the third gate electrode) is located between the first and second conductors (the gate electrodes of the first and second transistors);
and third wiring (bit lines 128) extending on the first conductor (indicated by callout 1), on the second conductor (callout 2), and on the third conductor (callout 3).
Atanasov lacks wherein the gap extends between the first conductor and the second conductor, between the first wiring and the second wiring, and between the third conductor and the third wiring.
However, Chien teaches creating an air gap surrounding the dielectric layer of a DRAM device to decrease parasitic capacitance. Replacing the spacer gap of Atanasov with an air gap around the semiconductors described by Chien would cause the gap to extend between the first conductor and the second conductor, between the first wiring and the second wiring, and between the third conductor and the third wiring.
It would have been obvious to a person of ordinary skill in the art before the time of filing to add the air gap of Chien to the semiconductor memory device of Atanasov to reduce parasitic capacitance, and thus improve the performance of the semiconductor memory device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure include: Chang et al. US 20220059546 A1, which discloses a dynamic random access memory including a plurality of word-line sets, a plurality of bit-line structures, a plurality of capacitors, a plurality of capacitor contacts, and a plurality of air gaps; Song et al. US 11,837,545 B2, which discloses a semiconductor memory device comprising active regions, spacers, and an air spacer; Teo et al. US 20210320106 A1, which discloses a DRAM device comprising a capacitor landing pad with a plurality of air gaps; and Wei et al. US 20220216210 A1, which discloses a DRAM including a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 3:30 pm.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818