DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 02/12/2026 in response to the Office Action mailed on 11/12/2025 is
being acknowledged and entered into the record. The present Final rejection is made by taking into fully
consideration all the amendments.
Response to Arguments
Applicant’s arguments, see page 8 of the remarks, filed on 02/12/2026, with respect to the 112(b) rejection of Claim 13 have been fully considered and are persuasive. The 112(b) rejection of Claim 13 has been withdrawn.
Applicant’s arguments, see pages 9-10 of the remarks, filed on 02/12/2026, with respect to the 102 rejection of Claim 1 and Claim 11 have been fully considered and are persuasive. Therefore, the rejection of Claims 1, 11 and their dependents has been withdrawn. However, upon further consideration, a new ground of 103 rejections is made in view of a different interpretation of previously applied prior art references of Xie in combination with Jain and newly found prior art reference of Jennings. A combination of these references teach the newly added limitations of Claim 1 and Claim 11 as noted in the rejection below.
On pages 10-11 of the remarks, filed on 02/12/2026, with regards to the 103 rejection of Claim 19, Applicant argues that the combination of Xie, Sun, Jain and Cheah fails to teach the limitation “wherein the first bridge chip and the second bridge chip are separate chips distinct from each other, and wherein the first region and the second region are configured to have different voltage levels”. These arguments have been fully considered and are persuasive. Therefore, the rejection of Claims 19 and its dependents has been withdrawn. However, upon further consideration, a new ground of 103 rejections is made in view of a different interpretation of previously applied prior art references of Xie in combination with Jain, Su, Cheah and newly found prior art reference of Jennings. A combination of these references teach the newly added limitations of Claim 19 as noted in the rejection below.
On page 11 of the remarks, filed on 02/12/2026, with regards to the 103 rejection of Claim 19, Applicant argues that Xie describes separated portions/regions within a single chip, which is different from the above-identified language of amended claim 19 where two distinct bridge chips are provided. This argument is fully considered but is not persuasive. In a different embodiment of Xie shown in Fig. 7, Xie teaches two sperate and distinct chips 110a, 110b. Therefore, Xie is still relied upon to teach this limitation of Claim 19.
On page 12 of the remarks, filed on 02/12/2026, with regards to the 103 rejection of Claim 19, Applicant argues that the relied upon bridge chip 110 of Jain is not two sperate chips but a single chip. This argument is fully considered but is not persuasive. The portions 111a and 111b of the bridge chip 110 shown in Fig. 1 of Jain are separate and distinct structures stacked vertically and comprise distinct circuitry and components, similar to the chips 310 and 320 of the instant application (see Fig. 2). Thus, the portions 111a and 111b can be broadly interpreted as sperate and distinct chips. Therefore, Jain is still relied upon to teach some of the limitations of Claim 19.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed either in a different embodiment of the primary reference or in the secondary reference(s).
Claims 1-5, 9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20200395300 A1), in view of Jain et al. (US 20190304915 A) and Jennings et al. (US 20210376834 A1).
Regarding Claim 1, Xie et al. discloses a semiconductor package comprising:
a substrate 102 having a cavity (see annotated Fig. 3: 102, paragraph 0022);
Note that the region of the substate 102 of Fig. 3 into which the bridge chip structure 110 is embedded is interpreted as the cavity.
a bridge chip structure 110 in the cavity of the substrate 102 and comprising a first bridge chip 110a and a second bridge chip 110b stacked on the first bridge chip 110a (see annotated Fig. 3: 110, 110a, 110b, paragraph 0023);
and a plurality of semiconductor chips 114-1, 114-2 spaced apart laterally on the substrate 102 (see annotated Fig. 3: 114-1, 114-2, 102, paragraph 0023),
wherein each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 comprises a first region R1 that is electrically connected to the first bridge chip 110a and a second region R2 that is electrically connected to the second bridge chip 110b (see annotated Fig. 3: R1, R2, 114-1, 114-2, 110a, 110b, paragraph 0023).
wherein the first bridge chip 110a and the second bridge chip 110b are separate chips distinct from each other,
wherein each of the first bridge chip 110a and the second bridge chip 110b stacked on the first bridge chip 110a comprises a capacitor 380 (Fig. 3: 380, paragraph 00343),
and wherein the first region R1 and the second region R2 are configured to have different voltage levels.
Xie et al., in a different embodiment, teaches the following limitation not disclosed in the previously referenced embodiment.
wherein the first bridge chip 110a and the second bridge chip 110b are separate chips distinct from each other (Fig. 7: 110a, 110b, paragraph 0047, 0048)
Therefore, it would have been obvious to a person of ordinary skill in the art to have combined the different embodiments of Xie et al. in order to have the first bridge chip and the second bridge chip as separate chips distinct from each other. Doing so would enable each chip to be fabricated, tested and replaced independently.
Jain et al. discloses a semiconductor package comprising the following limitation not disclosed in Xie et al.
wherein each of the first bridge chip 111a and the second bridge chip 111b stacked on the first bridge chip 111a comprises a capacitor 112 (see Fig. 1: 110, 111a, 111b, 112, paragraph 0032, 0033).
Note that the first portion 111a and the second portion 111b of the bridge chip structure 110 are separate and distinct portions stacked together similar to the chips 310 and 320 of the instant application (see Fig. 2), and are therefore interpreted as the first bridge chip and the second bridge chip respectively. Also note that the right-most region of the semiconductor chip 114-1 and the left-most region of the semiconductor chip 114-2 are interpreted as the second region.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Jain et al. in order to have each of the first bridge chip and the second bridge chip stacked on the first bridge chip comprises a capacitor. Doing so would improve the power delivering efficiency in the semiconductor package, as recognized by Jain et al. (paragraph 0026).
Jennings et al. discloses a semiconductor package comprising the following limitation not disclosed in Xie et al.
and wherein the first region and the second region (of the semiconductor chip 106) are configured to have different voltage levels (Fig. 2A: 106, paragraph 0041).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Jennings et al. in order to have the first region and the second region configured to have different voltage levels. By doing so, the semiconductor chip can be selectively configured to perform one or more user defined logic functions, as recognized by Jennings et al. (paragraph 00007).
Regarding Claim 2, the combination of Xie et al. and Jain et al. discloses the semiconductor package of claim 1, wherein:
the capacitor of the first bridge chip 110a includes a first capacitor 380 that is electrically connected to the first region R1 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 (as taught by Xie et al., see annotated Fig. 3: 380, paragraph 0034),
and the capacitor of second bridge chip 111b includes a second capacitor 112 that is electrically connected to the second region of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 (as taught by Jain et al., see Fig. 1: 110, 111a, 111b, 112, paragraph 0032, 0033).
Note that the right-most region of the semiconductor chip 114-1 and the left-most region of the semiconductor chip 114-2 are interpreted as the second region respectively.
Regarding Claim 3, the combination of Xie et al. and Jain et al. discloses the semiconductor package of claim 2, wherein each of the first capacitor 380 (as taught by Xie et al.) and the second capacitor 112 (as taught by Jain et al.) includes a metal-insulator-metal (MIM) capacitor, a deep trench capacitor (DTC), an integrated stack capacitor (ISC), or a combination thereof (see paragraph 0034 of Xie et al. and paragraph 0033 of Jain et al).
Regarding Claim 4, Xie et al. discloses the semiconductor package of claim 1, wherein the first region R1 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 overlaps the bridge chip structure 110 partially, and the second region R2 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 overlaps the bridge chip structure 110 completely (see annotated Fig. 3: R1, R2, 114-1, 114-2, 110).
Regarding Claim 5, Xie et al. discloses the semiconductor package of claim 1, further comprising a vertical connection structure 116 that surrounds the bridge chip structure 110 and includes a plurality of vertical connection layers at different levels, wherein the vertical connection structure 116 is electrically connected to the first region R1 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 (see annotated Fig. 3: 116, 114-1, 114-2, 110, paragraph 0031).
PNG
media_image1.png
763
1476
media_image1.png
Greyscale
Annotated Fig. 3 of Xie et al. (US Xie et al. (US 20200395300 A1)
Regarding Claim 9, Xie et al. discloses the semiconductor package of claim 1, wherein each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 includes a logic chip or a high bandwidth memory (HBM) chip (see paragraph 0027).
Regarding Claim 11, Xie et al. discloses a semiconductor package comprising:
a substrate 102 having a cavity (see annotated Fig. 3: 102, paragraph 0022);
Note that the region of the substate 102 of Fig. 3 into which the bridge chip structure 110 is embedded is interpreted as the cavity.
a vertical connection structure 116 comprising a plurality of vertical connection layers at different levels, the vertical connection structure 116 surrounding the bridge chip structure 110 (see annotated Fig. 3: 116, 110, paragraph 0031);
a bridge chip structure 110 in the cavity of the substrate 102 and comprising a first bridge chip 110a and a second bridge chip 110b stacked on the first bridge chip 110a (see annotated Fig. 3: 110, 110a, 110b, paragraph 0023);
Note that the first portion 110a and the second portion 110b of the bridge chip structure 110 are interpreted as the first bridge chip and the second bridge chip respectively.
a plurality of semiconductor chips 114-1, 114-2 spaced apart laterally on the substrate 102 (see annotated Fig. 3: 114-1, 114-2, 102, paragraph 0023),
and a connection bump structure 108 between the substrate 102 and each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 (see annotated Fig. 3: 108, 114-1, 114-2, 102, paragraph 0027),
the connection bump structure 108 comprising a plurality of first connection bumps 108-1 electrically connected to the vertical connection structure 116, a plurality of second connection bumps 108-2 each electrically connected to the bridge chip structure 110, and a plurality of third connection bumps 108-3 each electrically connected to the bridge chip structure 110 (see annotated Fig. 3: 108, 108-1, 108-2, 108-2, 110, paragraph 0027),
wherein each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 comprises a first region R1 electrically connected to the first bridge chip 110a and a second region R2 electrically connected to the second bridge chip 110b (see annotated Fig. 3: R1, R2, 114-1, 114-2, 110a, 110b, paragraph 0023),
wherein the first bridge chip 110a and the second bridge chip 110b are separate chips distinct from each other,
wherein each of the first bridge chip 110a and the second bridge chip 110b stacked on the first bridge chip 110a comprises a capacitor 380 (Fig. 3: 380, paragraph 00343),
and wherein the first region and the second region are configured to have different voltage levels.
Xie et al., in a different embodiment, teaches the following limitation not disclosed in the previously referenced embodiment.
wherein the first bridge chip 110a and the second bridge chip 110b are separate chips distinct from each other (Fig. 7: 110a, 110b, paragraph 0047, 0048)
Therefore, it would have been obvious to a person of ordinary skill in the art to have combined the different embodiments of Xie et al. in order to have the first bridge chip and the second bridge chip as separate chips distinct from each other. Doing so would enable each chip to be fabricated, tested and replaced independently.
Jain et al. discloses a semiconductor package comprising the following limitation not disclosed in Xie et al.
wherein each of the first bridge chip 111a and the second bridge chip 111b stacked on the first bridge chip 111a comprises a capacitor 112 (see Fig. 1: 110, 111a, 111b, 112, paragraph 0032, 0033).
Note that the first portion 111a and the second portion 111b of the bridge chip structure 110 are separate and distinct portions stacked together similar to the chips 310 and 320 of the instant application (see Fig. 2), and are therefore interpreted as the first bridge chip and the second bridge chip respectively. Also note that the right-most region of the semiconductor chip 114-1 and the left-most region of the semiconductor chip 114-2 are interpreted as the second region.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Jain et al. in order to have each of the first bridge chip and the second bridge chip stacked on the first bridge chip comprises a capacitor. Doing so would improve the power delivering efficiency in the semiconductor package, as recognized by Jain et al. (paragraph 0026).
Jennings et al. discloses a semiconductor package comprising the following limitation not disclosed in Xie et al.
and wherein the first region and the second region (of the semiconductor chip 106) are configured to have different voltage levels (Fig. 2A: 106, paragraph 0041).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Jennings et al. in order to have the first region and the second region configured to have different voltage levels. By doing so, the semiconductor chip can be selectively configured to perform one or more user defined logic functions, as recognized by Jennings et al. (paragraph 00007).
Regarding Claim 12, Xie et al. discloses the semiconductor package of claim 11, wherein each of the plurality of first connection bumps 108-1 is between the first region R1 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 and the vertical connection structure 116, and is electrically connected to the first region R1 (see annotated Fig. 3).
Regarding Claim 13, Xie et al. discloses the semiconductor package of claim 11, wherein each of the plurality of second connection bumps 108-2 is between the first region R1 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 and the bridge chip structure 110, and is electrically connected to the first region R1 (see annotated Fig. 3).
Regarding Claim 14, Xie et al. discloses the semiconductor package of claim 11, wherein each of the plurality of third connection bumps 108-3 is between the second region R2 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 and the bridge chip structure 110, and is electrically connected to the second region R2 (see annotated Fig. 3).
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20200395300 A1), in view of Jain et al. (US 20190304915 A) and Jennings et al. (US 20210376834 A1), as applied to Claim 1 above, further in view of Cheah et al. (US 20210005547 A1).
Regarding Claim 6, Xie et al. fails to teach the semiconductor package of claim 1, wherein the second bridge chip includes a through silicon via (TSV) that extends through the second bridge chip and extends to the first bridge chip, and the first bridge chip is electrically connected to the first region of each semiconductor chip of the plurality of semiconductor chips through the TSV.
However, Cheah et al. discloses a semiconductor package comprising a first chip 20 and a second chip 30, wherein the second chip 30 includes a through silicon via (TSV) 32 that extends through the second bridge chip 30 and extends to the first bridge chip 20 (see Fig. 1: 20, 30, 32, paragraph 0026, 0028).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Cheah et al. in order to have the second bridge chip include a through silicon via (TSV) that extends through the second bridge chip and extends to the first bridge chip. Doing so would establish electrical communication between first bridge chip and the plurality of semiconductor chips, as recognized by Cheah et al. (paragraph 0026).
Furthermore, Xie et al. teaches the first bridge chip 110a is electrically connected to the first region R1 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 through vias (black vertical lines of Fig. 3). Therefore, a person of ordinary skill in the art would have recognized that when the chip structure including the TSV of Cheah et al. is disposed in the semiconductor package of Xie et al., the first bridge chip will be electrically connected to the first region of each semiconductor chip of the plurality of semiconductor chips through the TSV.
Regarding Claim 7, Xie et al. fails to teach the semiconductor package of claim 1, wherein the first bridge chip includes a first bridge circuit that electrically connects the first regions of the plurality of semiconductor chips.
However, Cheah et al. discloses a semiconductor package, wherein the first chip 20 includes a first circuit 21 (See Fig. 1: 21, 20, paragraph 0056).
Note that the active surface 21 that includes both semiconductor devices and metallization is interpreted as the circuitry.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Cheah et al. in order to have the first bridge chip include a first bridge circuit. Doing so would enable faster communication between chips yielding better electrical performance.
Furthermore, a person of ordinary skill in the art would have recognized that when the chip structure including the first circuit of Cheah et al. is disposed in the semiconductor package of Xie et al., the first bridge circuit can be electrically connected to the first regions of the plurality of semiconductor chips.
Regarding Claim 8, Xie et al. fails to teach the semiconductor package of claim 1, wherein the second bridge chip includes a second bridge circuit that electrically connects the second regions of the plurality of semiconductor chips.
However, Cheah et al. discloses a semiconductor package, wherein the second chip 30 includes a second circuit 31 (See Fig. 1: 21, 20, paragraph 0056).
Note that the active surface 31 that includes both semiconductor devices and metallization is interpreted as the circuitry.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Cheah et al. in order to have the second bridge chip include a second bridge circuit. Doing so would enable faster communication between chips yielding better electrical performance.
Furthermore, a person of ordinary skill in the art would have recognized that when the chip structure including the first circuit of Cheah et al. is disposed in the semiconductor package of Xie et al., the second bridge circuit can be electrically connected to the second regions of the plurality of semiconductor chips.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20200395300 A1), in view of Jain et al. (US 20190304915 A) and Jennings et al. (US 20210376834 A1), as applied to Claim 1 above, further in view of Sun et al. (US 20220270976 A1).
Regarding Claim 10, Xie et al. fails to teach the semiconductor package of claim 1, further comprising an encapsulation layer on the substrate that surrounds the bridge chip structure.
However, Sun et al. teaches a semiconductor package comprising an encapsulation layer 183 on the substrate 102 that surrounds the bridge chip structure 110 (see Fig. 13: 183, 102, 110, paragraph 0048).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Sun et al. in order to have an encapsulation layer on the substrate that surrounds the bridge chip structure. Doing so would protect the bridge chip structure from external contaminants.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20200395300 A1), in view of Jain et al. (US 20190304915 A) and Jennings et al. (US 20210376834 A1), as applied to Claim 11 above, further in view of Darmawikarta et al. (US 20230197661 A1).
Regarding Claim 15, Xie et al. fails to teach the semiconductor package of claim 11, wherein the plurality of first connection bumps are horizontally spaced apart from each other by a first pitch, and wherein the first pitch is about 130 μm to about 170 μm.
However, Darmawikarta et al. teaches a semiconductor package, wherein the plurality of first connection bumps 130-1 are horizontally spaced apart from each other by a first pitch, and wherein the first pitch is about 75 μm to about 200 μm (see annotated Fig. 1: 130-1, paragraph 0026, 0021).
Note that according to Fig. 1, the plurality of first connection bumps 130-1 share the same pitch as the vertical pillars 152, which has a pitch in the range of 75 μm to about 200 μm.
According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Xie et al. and Darmawikarta et al. in order to have the plurality of first connection bumps horizontally spaced apart from each other by a first pitch, and wherein the first pitch is about 130 μm to about 170 μm. Doing so would optimize the pitch dimension such that they are not too large that result in wasted area and not too small that they introduce short circuit, stress and manufacturing defects.
Regarding Claim 16, Xie et al. fails to teach the semiconductor package of claim 11, wherein the plurality of third connection bumps are horizontally spaced apart from each other by a second pitch, and wherein the second pitch is about 45 μm to about 65 μm.
However, Darmawikarta et al. teaches a semiconductor package, wherein the plurality of third connection bumps 130-3 are horizontally spaced apart from each other by a second pitch, and wherein the second pitch is about 7 μm to about 100 μm (see annotated Fig. 1: 130-3, paragraph 0021, 0035).
According to MPEP § 2144.05 (I), “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists”. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Xie et al. and Darmawikarta et al. in order to have the plurality of third connection bumps horizontally spaced apart from each other by a second pitch, and wherein the second pitch is about 45 μm to about 65 μm. Doing so would optimize the pitch dimension such that they are not too large that result in wasted area and not too small that they introduce short circuit, stress and manufacturing defects.
Regarding Claim 17, Xie et al. fails to teach the semiconductor package of claim 11, wherein each of the plurality of first connection bumps is larger than each of the plurality of second connection bumps and each of the plurality of third connection bumps.
However, Darmawikarta et al. teaches a semiconductor package, wherein each of the plurality of first connection bumps 130-1 is larger than each of the plurality of second connection bumps 130-2 and each of the plurality of third connection bumps 130-3 (see annotated Fig. 1: 130-1, 130-2, 130-3).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Xie et al. and Darmawikarta et al. in order to have each of the plurality of first connection bumps larger than each of the plurality of second connection bumps and each of the plurality of third connection bumps. Doing so would yield high reliability for power delivery enabled by the larger bumps and high-density interconnection rendered by the smaller bumps.
PNG
media_image2.png
1073
1853
media_image2.png
Greyscale
Annotated Fig. 1 of Darmawikarta et al. (US 20230197661 A1)
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20200395300 A1), in view of Jain et al. (US 20190304915 A) and Jennings et al. (US 20210376834 A1), as applied to Claim 11 above, in view of Cheah et al. (US 20210005547 A1).
Regarding Claim 18, Xie et al. fails to teach the semiconductor package of claim 11, wherein the second bridge chip includes a through silicon via (TSV) that extends through the second bridge chip and extends to the first bridge chip, and wherein the first bridge chip is electrically connected to each of the plurality of second connection bumps through the TSV.
However, Cheah et al. discloses a semiconductor package comprising a first chip 20 and a second chip 30, wherein the second chip 30 includes a through silicon via (TSV) 32 that extends through the second bridge chip 30 and extends to the first bridge chip 20 (see Fig. 1: 20, 30, 32, paragraph 0026, 0028).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Cheah et al. in order to have the second bridge chip include a through silicon via (TSV) that extends through the second bridge chip and extends to the first bridge chip. Doing so would establish electrical communication between first bridge chip and the plurality of semiconductor chips, as recognized by Cheah et al. (paragraph 0026).
Furthermore, Xie et al. teaches the first bridge chip 110a is electrically connected to the first region R1 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 through vias (black vertical lines of Fig. 3). Therefore, a person of ordinary skill in the art would have recognized that when the chip structure including the TSV of Cheah et al. is disposed in the semiconductor package of Xie et al., the first bridge chip will be electrically connected to the first region of each semiconductor chip of the plurality of semiconductor chips through the TSV.
Claim 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20200395300 A1), in view of Jain et al. (US 20190304915 A), Jennings et al. (US 20210376834 A1), Sun et al. (US 20220270976 A1) and Cheah et al. (US 20210005547 A1).
Regarding Claim 19, Xie et al. teaches a semiconductor package comprising:
a substrate 102 having a cavity (see annotated Fig. 3: 102, paragraph 0022);
Note that the region of the substate 102 of Fig. 3 into which the bridge chip structure 110 is embedded is interpreted as the cavity.
a bridge chip structure 110 in the cavity of the substrate 102 and comprising a first bridge chip 110a and a second bridge chip 110b stacked on the first bridge chip 110a (see annotated Fig. 3: 110, 110a, 110b, paragraph 0023);
Note that the first portion 110a and the second portion 110b of the bridge chip structure 110 are interpreted as the first bridge chip and the second bridge chip respectively.
an encapsulation layer on the substrate that surrounds the bridge chip structure;
a plurality of semiconductor chips 114-1, 114-2 spaced apart laterally on the substrate 102 and each comprising a logic chip or a high bandwidth memory (HBM) chip (see annotated Fig. 3: 114-1, 114-2, 102, paragraph 0023, 0027),
and a vertical connection structure 116 that surrounds the bridge chip structure 110 and including a plurality of vertical connection layers at different levels (see annotated Fig. 3: 116, 110, paragraph 0031),
wherein each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 comprises a first region R1 that is electrically connected to the first bridge chip 110a and a second region R2 that is electrically connected to the second bridge chip 110b (see annotated Fig. 3: R1, R2, 114-1, 114-2, 110a, 110b, paragraph 0023).
wherein the first region R1 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 overlaps the bridge chip structure 110 partially, and the second region R2 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 overlaps the bridge chip structure 110 completely (see annotated Fig. 3: R1, R2, 114-1, 114-2, 110),
wherein the first bridge chip 110a includes a first capacitor 380 that is electrically connected to the first region R1 of each of the plurality of semiconductor chips 114-1, 114-2 (see annotated Fig. 3: 380, paragraph 0034),
the second bridge chip comprises a second capacitor that is electrically connected to the second region of each of the plurality of semiconductor chips,
and each of the first capacitor 380 and the second capacitor comprises a metal-insulator-metal (MIM) capacitor, a deep trench capacitor (DTC), an integrated stack capacitor (ISC), or a combination thereof (paragraph 0034),
wherein the second bridge chip includes a through silicon via (TSV) that extends through the second bridge chip and extends to the first bridge chip, and the first bridge chip is electrically connected to the first region of each of the plurality of semiconductor chips through the TSV.
and wherein the vertical connection structure 116 is electrically connected to the first region R1 of each of the plurality of semiconductor chips 114-1, 114-2 (see annotated Fig. 3: 116. R1, 114-1, 114-2).
wherein the first bridge chip 110a and the second bridge chip 110b are separate chips distinct from each other,
and wherein the first region R1 and the second region R2 are configured to have different voltage levels.
However, Sun et al. teaches a semiconductor package comprising an encapsulation layer 183 on the substrate 102 that surrounds the bridge chip structure 110 (see Fig. 13: 183, 102, 110, paragraph 0048).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Sun et al. in order to have an encapsulation layer on the substrate that surrounds the bridge chip structure. Doing so would protect the bridge chip structure from external contaminants.
Furthermore, Jain et al. discloses a semiconductor package bridge chip structure 110 comprising a first bridge chip 111a and a second bridge chip 111b, wherein the second bridge chip 111b comprises a second capacitor 112 that is electrically connected to the second region of each of the plurality of semiconductor chips 114-1, 114-2, and the second capacitor 112 comprises a metal-insulator-metal (MIM) capacitor, a deep trench capacitor (DTC), an integrated stack capacitor (ISC), or a combination thereof (see Fig. 1: 110, 111a, 111b, 112, paragraph 0032, 0033).
Note that the first portion 111a and the second portion 111b of the bridge chip structure 110 are interpreted as the first bridge chip and the second bridge chip respectively. Also note that the right-most region of the semiconductor chip 114-1 and the left-most region of the semiconductor chip 114-2 are interpreted as the second region.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Jain et al. in order to come up with the claimed invention. Doing so would improve the power delivering efficiency in the semiconductor package, as recognized by Jain et al. (paragraph 0026).
Cheah et al. discloses a semiconductor package comprising a first chip 20 and a second chip 30, wherein the second chip 30 includes a through silicon via (TSV) 32 that extends through the second bridge chip 30 and extends to the first bridge chip 20 (see Fig. 1: 20, 30, 32, paragraph 0026, 0028).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Cheah et al. in order to have the second bridge chip include a through silicon via (TSV) that extends through the second bridge chip and extends to the first bridge chip. Doing so would establish electrical communication between first bridge chip and the plurality of semiconductor chips, as recognized by Cheah et al. (paragraph 0026).
Furthermore, Xie et al. teaches the first bridge chip 110a is electrically connected to the first region R1 of each semiconductor chip of the plurality of semiconductor chips 114-1, 114-2 through vias (black vertical lines of Fig. 3). Therefore, a person of ordinary skill in the art would have recognized that when the chip structure including the TSV of Cheah et al. is disposed in the semiconductor package of Xie et al., the first bridge chip will be electrically connected to the first region of each of the plurality of semiconductor chips through the TSV.
Xie et al., in a different embodiment, teaches the following limitation not disclosed in the previously referenced embodiment.
wherein the first bridge chip 110a and the second bridge chip 110b are separate chips distinct from each other (Fig. 7: 110a, 110b, paragraph 0047, 0048)
Therefore, it would have been obvious to a person of ordinary skill in the art to have combined the different embodiments of Xie et al. in order to have the first bridge chip and the second bridge chip as separate chips distinct from each other. Doing so would enable each chip to be fabricated, tested and replaced independently.
Jennings et al. discloses a semiconductor package comprising the following limitation not disclosed in Xie et al.
and wherein the first region and the second region (of the semiconductor chip 106) are configured to have different voltage levels (Fig. 2A: 106, paragraph 0041).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Jennings et al. in order to have the first region and the second region configured to have different voltage levels. By doing so, the semiconductor chip can be selectively configured to perform one or more user defined logic functions, as recognized by Jennings et al. (paragraph 00007).
Regarding Claim 20, Xie et al. fails to teach the semiconductor package of claim 19, wherein the first bridge chip includes a first bridge circuit that electrically connects the first regions of the plurality of semiconductor chips, and wherein the second bridge chip includes a second bridge circuit that electrically connects the second regions of the plurality of semiconductor chips.
However, Cheah et al. teaches wherein the first chip 20 includes a first circuit 21 and wherein the second chip 30 includes a second circuit 31 (see Fig. 1: 20, 30, 21, 31, paragraph 0056).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of both Xie et al. and Cheah et al. in order to have the first bridge chip include a first bridge circuit and the second bridge chip include a second bridge circuit. Doing so would enable faster communication between chips yielding better electrical performance.
Furthermore, a person of ordinary skill in the art would have recognized that the chip structure of Cheah et al. can be disposed in the semiconductor package of Xie et al., such that the first bridge circuit electrically connects the first regions of the plurality of semiconductor chips and the second bridge circuit that electrically connects the second regions of the plurality of semiconductor chips.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 05/21/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights