DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/18/2026.
Applicant’s election without traverse of Species I, claims 1-17 in the reply filed on 6/18/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 6 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the second sidewall of the first dummy pad" in line 14. There is insufficient antecedent basis for these limitations in the claim.
Claim 6 depends from claim 5 and is indefinite for the same reasons as claim 5
Claim 5 recites the limitation "the second sidewall of the first dummy pad" in line 14, whereas in line 7, it is defined that “the second dummy pad includes a second sidewall adjacent to the second semiconductor chip”. Therefore, it is not clear “the second sidewall” belongs to the first dummy pad or the second dummy pad. Accordingly, the boundaries of the claims are not reasonably clear and also language in the claims is ambiguous, vague, incoherent, opaque, or otherwise unclear in describing and defining the claimed invention. Note; For the purpose of examination, the examiner interprets the limitation "the second sidewall of the first dummy pad" as "the second sidewall of the second dummy pad".
Claim 7 recites the limitation " the first direction " in line 2. There is insufficient antecedent basis for these limitations in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-12, 14 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHOI, US 2022/0013497.
Regarding claim 10, CHOI discloses; A semiconductor package comprising: a substrate (Fig.1-12 and [0017]; substrate 400); a substrate pad on the substrate (Fig.1-12 and [0038]; pad 420 formed on the substrate 400); a first semiconductor chip and a second semiconductor chip on the substrate and adjacent to each other (Fig.1-12 and [0017]; a first semiconductor chip 100, a second semiconductor chip 200 arranged on the substrate 400); a connective terminal between the substrate pad and the first semiconductor chip (Fig.1-12 and [0026]; first connection member 130 formed between the active surface of the first semiconductor substrate 110 and the package substrate 400); and between the substrate pad and the second semiconductor chip (Fig.1-12 and [0033]; second connection member 230 formed between the active surface of the second connection pad 220 and the package substrate 400); a dummy pad on the substrate and spaced apart from the substrate pad, wherein the dummy pad is between the first semiconductor chip and the second semiconductor chip (Fig.1-12 and [0017]; dummy pad DP is between first semiconductor chip 100 and second semiconductor chip 200 and spaced apart from pad 420); and an underfill material layer interposed between the substrate and the first semiconductor chip and between the substate and the second semiconductor chip, wherein the underfill material layer extends along the dummy pad (Fig. 9 and [0076]; under-fill 510 is between substrate 400 and first semiconductor chip 100 and between substrate 400 and second semiconductor chip 200), wherein in a plan view of the semiconductor package, the dummy pad overlaps at least a portion of the first semiconductor chip and at least a portion of the second semiconductor chip (Fig.1-12 and [0051]; the dummy pad DP is disposed on the package substrate 400 to at least partially overlap the first semiconductor chip 100, the second semiconductor chip 200 in the X direction).
Regarding claim 11, CHOI discloses; in a plan view of the semiconductor package, the dummy pad has a rectangular, circular, polygonal or oval shape (Fig.1-12 and [0017]; dummy pad DP is between first semiconductor chip 100 and second semiconductor chip 200 is rectangular shaped).
Regarding claim 12, CHOI discloses; the dummy pad includes: a first dummy pad overlapping at least a portion of the first semiconductor chip in a plan view of the package (attached Fig. 8 below); and a second dummy pad overlapping at least a portion of the second semiconductor chip in the plan view (attached Fig. 8 below).
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Regarding claim 14, CHOI discloses; the first semiconductor chip includes a first chip pad (Fig.1-12 and [0025]; first semiconductor chip 100 includes a first connection pad 120), wherein the second semiconductor chip includes a second chip pad (Fig.1-12 and [0032]; second semiconductor chip 200 include a second semiconductor substrate 210, a second connection pad 220), wherein the connective terminal is in contact with the first chip pad of the first semiconductor chip and the substrate pad of the substrate, and is in contact with the second chip pad of the second semiconductor chip and the substrate pad on the substrate (Fig.1-12 and [0026]; first connection member 130 formed between the active surface of the first semiconductor substrate 110 and the package substrate 400).
Regarding claim 17, CHOI discloses; the first semiconductor chip and the second semiconductor chip are adjacent to each other in a first direction (attached Fig. 8 below), wherein the dummy pad includes dummy pads between the first semiconductor chip and the second semiconductor chip and arranged along a second direction intersecting the first direction (attached Fig. 8 below).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI, US 2022/0013497, in view of OH, US 2022/0328439.
Regarding claims 1 and 2, CHOI discloses in claim 1; a semiconductor package comprising: a substrate (Fig.1-12 and [0017]; substrate 400); a substrate pad on the substrate (Fig.1-12 and [0038]; pad 420 formed on the substrate 400); a first semiconductor chip and a second semiconductor chip on the substrate (Fig.1-12 and [0017]; a first semiconductor chip 100, a second semiconductor chip 200 arranged on the substrate 400); a connective terminal between the substrate pad and the first semiconductor chip (Fig.1-12 and [0026]; first connection member 130 formed between the active surface of the first semiconductor substrate 110 and the package substrate 400); and between the substrate pad and the second semiconductor chip (Fig.1-12 and [0033]; second connection member 230 formed between the active surface of the second connection pad 220 and the package substrate 400); a dummy pad on the substrate, and spaced apart from the substrate pad, wherein the dummy pad is between the first semiconductor chip and the second semiconductor chip (Fig.1-12 and [0017]; dummy pad DP is between first semiconductor chip 100 and second semiconductor chip 200 and spaced apart from pad 420); and an underfill material layer interposed between the substrate and the first semiconductor chip and between the substrate and the second semiconductor chip (Fig. 9 and [0076]; under-fill 510 is between substrate 400 and first semiconductor chip 100 and between substrate 400 and second semiconductor chip 200). CHOI substantially discloses the invention including a dummy pad disposed between the semiconductor chips but is silent about the dummy pad and the substrate pad comprise a same material in claim 1 and a top face of the dummy pad is coplanar with a top face of the substrate pad in claim 2. However, OH teaches that the first upper power pad P12, the dummy pad DMP, and the first pad 141 coplanar with each other and made of the same material, and formed using the same process ( Fig.7 and [0095]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify CHOI by providing the dummy pad and the substrate pad comprise a same material in claim 1 and a top face of the dummy pad is coplanar with a top face of the substrate pad in claim 2, so that to provide a display device with improved bonding reliability between the printed circuit film and the pads of the display panel ([0008]).
Regarding claim 3, CHOI discloses; the underfill material layer is on the dummy pad (Fig. 9 and [0076]; under-fill 510 is on the dummy pad DP).
Regarding claim 4, CHOI discloses; the first semiconductor chip and the second semiconductor chip are adjacent to each other in a first direction (Fig.1-12 and [0017]; first semiconductor chip 100 and second semiconductor chip 200 are adjacent to each other in the X direction), wherein the dummy pad has a first sidewall and a second sidewall opposite to each other in the first direction (Fig.1-12 and [0017]; dummy pad DP has right and left sidewall opposite to each other in the X direction), wherein the first semiconductor chip has a third sidewall (Fig.1-12 and [0017]; left sidewall of first semiconductor chip 100), wherein the second semiconductor chip has a fourth sidewall facing the third sidewall (Fig.1-12 and [0017]; right sidewall of second semiconductor chip 200 facing the left sidewall of first semiconductor chip 100), wherein the first sidewall of the dummy pad is aligned with the third sidewall of the first semiconductor chip in a vertical direction or is under the first semiconductor chip (Fig.1-2 and [0017]; right sidewall of dummy pad DP is under the left sidewall of first semiconductor chip 100), wherein the second sidewall of the dummy pad is aligned with the fourth sidewall of the first semiconductor chip in the vertical direction or is under the second semiconductor chip (Fig.1-2 and [0017]; left sidewall of dummy pad DP is under the right sidewall of first semiconductor chip 100).
Regarding claim 7, CHOI discloses; the first semiconductor chip and the second semiconductor chip are adjacent to each other in the first direction (Fig.1-12 and [0017]; first semiconductor chip 100 and second semiconductor chip 200 are adjacent to each other in the X direction), wherein a spacing in the first direction between the first semiconductor chip and the second semiconductor chip is smaller than or equal to a width in the first direction of the dummy pad (Fig.1-12 and [0051]; the dummy pad DP is disposed on the package substrate 400 to at least partially overlap the first semiconductor chip 100, the second semiconductor chip 200 in the X direction).
Regarding claim 8, CHOI discloses; the substrate includes a redistribution insulating layer and a redistribution pattern in the redistribution insulating layer (Fig.12 and [0092]; top redistribution insulating layer 610 and redistribution conductive layers 630).
Regarding claim 9, CHOI discloses; the substrate includes: a base layer (Fig.12 and [0092]; bottom redistribution insulating layer 610 and redistribution conductive layers 630); a wiring insulating layer on the base layer (Fig.12 and [0092]; top redistribution insulating layer 610 and redistribution conductive layers 630); a wiring pattern in the wiring insulating layer (Fig.12 and [0092]; redistribution conductive layers 630 at the top redistribution insulating layer 610); a through electrode extending through the base layer and electrically connected to the wiring pattern (Fig.12 and [0092]; redistribution vias 641 electrically connected to the redistribution conductive layers 630).
Claim(s) 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI, US 2022/0013497, in view of OH, US 2022/0328439 as applied to claims 1-4 and 7-9 above, and further in view of Shih, US 10529690.
Regarding claims 5 and 6, CHOI discloses in claim 5; the first semiconductor chip and the second semiconductor chip are adjacent to each other in a first direction (attached Fig. 8 below), wherein the dummy pad includes a first dummy pad and a second dummy pad adjacent to each other (attached Fig. 8 below), wherein the first dummy pad includes a first sidewall adjacent to the first semiconductor chip (attached Fig. 8 below), wherein the second dummy pad includes a second sidewall adjacent to the second semiconductor chip (attached Fig. 8 below), wherein the first semiconductor chip includes a third sidewall (attached Fig. 8 below), wherein the second semiconductor chip includes a fourth sidewall facing the third sidewall of the first semiconductor chip (attached Fig. 8 below), wherein the first sidewall of the first dummy pad is aligned with the third sidewall of the first semiconductor chip in a vertical direction or is under the first semiconductor chip (attached Fig. 8 below), wherein the second sidewall of the first dummy pad is aligned with the fourth sidewall of the second semiconductor chip in the vertical direction or is under the second semiconductor chip (attached Fig. 8 below). CHOI in view of OH, substantially discloses the invention including first semiconductor chip and second semiconductor chip are adjacent to each other in the X direction and first and second dummy pad disposed between the first and second semiconductor chips in the Y direction but is silent about first and second dummy pad adjacent to each other in the first direction in claim 5 and the dummy pad further includes a third dummy pad between the first dummy pad and the second dummy pad in claim 6. However, Shih teaches that dummy structures adjacent to each other in the same direction as adjacent top and bottom dies 68, also teaches a third dummy structure between two top and bottom dummy structure (Fig. 6C, 7;106,104). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify CHOI in view of OH by providing first and second dummy pad adjacent to each other in the first direction in claim 5 and the dummy pad further includes a third dummy pad between the first dummy pad and the second dummy pad in claim 6, so that dummy die structures adjacent the active dies to reduce the warpage of the package structure. This reduction of the warpage of the package structure enables a more reliable package structure by reducing the likelihood of cold joints between the active dies and the interposer (Col 2; Line 17-21).
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Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over CHOI, US 2022/0013497, as applied to claims 10-12, 14 and 17 above, and further in view of Shih, US 10529690.
Regarding claim 13, CHOI substantially discloses the invention including first semiconductor chip and second semiconductor chip are adjacent to each other in the X direction and first and second dummy pad disposed between the first and second semiconductor chips but is silent about the dummy pad further includes a third dummy pad between the first dummy pad and the second dummy pad. However, Shih teaches that dummy structures adjacent to each other in the same direction as adjacent top and bottom dies 68, also teaches a third dummy structure between two top and bottom dummy structure (Fig. 6C, 7;106,104). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify CHOI in view of OH by providing the dummy pad further includes a third dummy pad between the first dummy pad and the second dummy pad, so that the dummy dies can prevent warpage is to reduce the coefficient of thermal expansion (CTE) mismatch between the components (Col 9; Line 3-5).
Claim(s) 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over CHOI, US 2022/0013497, as applied to claims 10-12, 14 and 17 above, and further in view of OH, US 2022/0328439.
Regarding claims 15-16, CHOI substantially discloses the invention including a dummy pad disposed between the semiconductor chips but is silent about a thickness of the dummy pad on the substrate is substantially equal to a thickness of the substrate pad on the substrate in claim 15 and the dummy pad and the substrate pad comprise a same material in claim 16. However, OH teaches that the first upper power pad P12, the dummy pad DMP, and the first pad 141 coplanar with each other and made of the same material, and formed using the same process ( Fig.7 and [0095]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify CHOI by providing a thickness of the dummy pad on the substrate is substantially equal to a thickness of the substrate pad on the substrate in claim 15 and the dummy pad and the substrate pad comprise a same material in claim 16, so that to provide a display device with improved bonding reliability between the printed circuit film and the pads of the display panel ([0008]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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