DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lane et al. (Lane, US 20158/0206854 A1).
Regarding claim 1, Lane shows an integrated device comprising: a bottom substrate (first substrate 206 in FIG. 13) comprising first conductors ( electrical path 1300 in FIG. 13); a top substrate (second substrate 205) comprising second conductors (electrical path 1300); a first die ( first die 208) disposed between the bottom substrate (first substrate 206) and the top substrate (second substrate 205), the first die ( first die 208) including circuitry and first contacts ( set of interconnects 218) electrically connected to the circuitry and to the first conductors (electrical path 1300); and a redistribution die (redistribution portion in Fig. 13) disposed between the bottom substrate (first substrate 206) and the top substrate (second substrate 205) adjacent to the first die ( die 208), the redistribution die including: second contacts ( interconnects 228) electrically connected to the first contacts through the first conductors ( electrical path 1300); third contacts(interconnect 228) electrically connected to the second conductors (electrical path 1300); and redistribution traces (Redistribution portion in FIG. 13) electrically connected to the second contacts and to the third contacts; and wherein the top substrate includes fourth contacts electrically connected through the second conductors to the third contacts to define one or more signal paths between the fourth contacts and the first die (see FIG. 13 and related text).
Regarding claim 2, Lane shows an integrated device comprising, wherein the redistribution die (Redistribution Portion in FIG. 13) comprises a semiconductor die (die 239/237/209/207), and wherein the redistribution traces are integrated within the semiconductor die (see Fig. 13).
Regarding claim 3, Lane shows an integrated device, further comprising: interconnect conductors (conductor 215) disposed between the bottom substrate (first substrate 206) and the top substrate (second substrate 205) and defining a portion of the one or more signal paths between the fourth contacts and the first die (die 208).
Regarding claim 4, Lane shows an integrated device comprising, wherein at least one of the interconnect conductors ( electrical path 1300) is integrated within the redistribution die (Redistribution Portion in FIG. 13).
Regarding claim 5, Lane shows an integrated device comprising, wherein at least one of the interconnect conductors (conductor 1302) is external to the redistribution die (Redistribution Portion in FGI. 13) and electrically connected, through the first conductors (electrical path 1300), to the third contacts of the redistribution die.
Regarding claim 6, Lane shows an integrated device comprising, wherein the fourth contacts (contact 249) are configured to be coupled to a second die (die 239) comprising second circuitry ( die 239).
Regarding claim 7, Lane shows an integrated device comprising, wherein the circuitry of the first die defines one or more processor cores and the second circuitry of the second die defines one or more memory cells ([0049]).
Regarding claim 8, Lane shows an integrated device further comprising one or more additional redistribution dies (Redistribution Portion in FIG. 13) disposed between the bottom substrate (first substrate 206) and the top substrate (second substrate 205) adjacent to the first die and configured to define one or more additional signal paths between the first die and the fourth contacts (see FIG. 13).
Regarding claim 9, Lane shows an integrated device further comprising a second redistribution die (Redistribution Portion in FIG. 13) disposed between the bottom substrate (first substrate 206) and the top substrate (second substrate 205) on an opposite side of the first die from the redistribution die, the second redistribution die configured to define portions of second signal paths between the first die and the fourth contacts ( FIG. 13).
Regarding claim 10, Lane shows an integrated device further comprising a third redistribution die disposed between the bottom substrate and the top substrate and configured to define portions of third signal paths between the first die and the fourth contacts (see FIG. 13).
Regarding claim 11, Lane shows an integrated device, further comprising a fourth redistribution die ( Redistribution Portion in FIG. 13) disposed between the bottom substrate (first substrate 206) and the top substrate (substrate 205) and configured to define portions of fourth signal paths between the first die and the fourth contacts (see FIG. 13).
Regarding claim 12, Lane shows an integrated device comprising, wherein the first die (substrate 206) and a second die (substrate 205) coupled to the fourth contacts are integrated in a package-on-package configuration (FIG. 13).
Regarding claim 13, Lane shows a method of fabricating an integrated device (device 200 in FGI. 13), the method comprising: coupling a first die ( die 208) to a bottom substrate (substrate 206), wherein coupling the first die (die 208 in FIG. 13) to the bottom substrate (substrate 206) includes electrically connecting first contacts ( contact set 218) of the first die to first conductors of the bottom substrate (substrate 206); and coupling a redistribution die (Redistribution Portion in FIG. 13) to the bottom substrate adjacent to the first die, wherein coupling the redistribution die to the bottom substrate includes: electrically connecting second contacts of the redistribution die to the first contacts through the first conductors; and electrically connecting third contacts of the redistribution die to second conductors of a top substrate to define one or more signal paths between the first die and a first subset of fourth contacts of the top substrate (see FIG. 13).
Regarding claim 14, Lane shows a method of fabricating an integrated device (device 200 in FGI. 13), wherein the redistribution die comprises a semiconductor die (die 208), and wherein the second contacts, the third contacts, and redistribution traces therebetween are integrated within the semiconductor die (see FIG. 13).
Regarding claim 15, Lane shows a method of fabricating an integrated device (device 200 in FGI. 13), further comprising coupling a second die (die 239) to the fourth contacts of the top substrate (substrate 205).
Regarding claim 16, Lane shows a method of fabricating an integrated device (device 200 in FGI. 13), further comprising, wherein the first die includes first circuitry defining one or more processor cores and the second die includes second circuitry defining one or more memory cells (see FIG. 13).
Regarding claim 17, Lane shows a method of fabricating an integrated device (device 200 in FGI. 13), further comprising, electrically connecting interconnect conductors to the second conductors of the top substrate, wherein the interconnect conductors are electrically connected to the third contacts of the redistribution die (see FIG. 13 and related text).
Regarding claim 18, Lane shows a method of fabricating an integrated device (device 200 in FGI. 13), wherein at least one of the interconnect conductors is integrated within the redistribution die (Fig. 13).
Regarding claim 19, Lane shows a method of fabricating an integrated device (device 200 in FGI. 13), wherein at least one of the interconnect conductors is external to the redistribution die and electrically connected, through the first conductors, to the third contacts of the redistribution die (see FIG. 13 and related text).
Regarding claim 20, Lane shows a method of fabricating an integrated device (device 200 in FGI. 13), wherein disposing one or more additional redistribution dies on the bottom substrate adjacent to the first die; and electrically connecting the one or more additional redistribution dies between the first die and the fourth contacts to define one or more additional signal paths between the first die and a second subset of the fourth contacts of the top substrate (see FIG. 13 and related text).
Regarding claim 21, Lane shows a device (device 200 in FIG. 13) comprising: a bottom substrate (substrate 206) comprising first conductors ( conductor 1300); a top substrate (substrate 205) comprising second conductors (conductor 1300); a first die (die 208) disposed between the bottom substrate (substrate 206) and the top substrate (substrate 205), the first die including circuitry and first contacts ( contact set 218) electrically connected to the circuitry and to the first conductors (conductor 1300); a redistribution die disposed between the bottom substrate and the top substrate, the redistribution die including: second contacts electrically connected to the first contacts through the first conductors; third contacts electrically connected to the second conductors; and redistribution traces electrically connected to the second contacts and to the third contacts; and a second die electrically connected to fourth contacts of the top substrate, wherein the fourth contacts are electrically connected through the second conductors to the third contacts to define one or more signal paths between the first die and the second die (see FIG. 13 and related text).
Regarding claim 22, Lane shows a device (device 200 in FIG. 13) comprising, wherein the redistribution die comprises a semiconductor die, and wherein the redistribution traces are integrated within the semiconductor die (see FIG. 13 and related text).
Regarding claim 23, Lane shows a device (device 200 in FIG. 13) further comprising interconnect conductors disposed between the bottom substrate and the top substrate and defining a portion of the one or more signal paths between the fourth contacts and the first die (see FIG. 13 and related text).
Regarding claim 24, Lane shows a device (device 200 in FIG. 13) comprising, wherein at least one of the interconnect conductors is integrated within the redistribution die (see FIG. 13 and related text).
Regarding claim 25, Lane shows a device (device 200 in FIG. 13) comprising, wherein at least one of the interconnect conductors is external to the redistribution die and electrically connected, through the first conductors, to the third contacts of the redistribution die (see FIG. 13 and related text).
Regarding claim 26, Lane shows a device (device 200 in FIG. 13) comprising, wherein the circuitry of the first die defines one or more processor cores, and wherein the second die includes second circuitry defining one or more memory cells (see FIG. 13 and related text).
Regarding claim 27, Lane shows a device (device 200 in FIG. 13) further comprising one or more additional redistribution dies disposed between the bottom substrate and the top substrate adjacent to the first die and configured to define one or more additional signal paths between the first die and the second die (see FIG. 13 and related text).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893