DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 05/20/2026 has been entered. Applicant's amendment have overcome
the Claims 112 (b) rejections previously set forth in the Non-Final Office Action dated on 02/26/2026. Claims 6-10, 12 and 20 are canceled. Claims 21-27 are new.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 05/20/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 20210210423 A1 to Chang, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 112
Claims 1, 14 and 18 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first
paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification as filed, fails to adequately describe the limitation of "wherein at least one the first or the second obtuse angles is greater than 120° and less than or equal to 130°”. The specification discloses in [0038], “the second lower pads 232 may be set to be about 100° or more” and in [0039], “the second lower pads 232 may be set to be about 130° or less”. Then, the disclosed range of the second lower pads 232 may be set to be about 100° to about 130° or less.
Claims 1, 14 and 18 includes a new matter, the specification and figs. 1A-12, none of the them discloses "wherein at least one the first or the second obtuse angles is greater than 120° and less than or equal to 130°”.
For the examination propose, the limitation of “wherein at least one the first or the second obtuse angles is greater than 120° and less than or equal to 130°” is interpreted as “wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 11, 13-17,21 and 26 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 20200135699 A1, of the record) in view of Watanabe (US 20210280545 A1, hereinafter Watanabe, of the record) and further in view of Chang et al. (US 20210210423 A1, hereinafter Chang).
Re: Independent Claim 1, Hwang discloses a semiconductor package (Fig. 1) comprising:
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Hwang’s Figure 2-Annotated.
a first semiconductor chip (100A semiconductor chip in [0021], Figs. 1,2) including a first substrate (110-bottom a semiconductor substrate in [0021], Figs. 1,2-Annotated), a first pad (154 a bonding pad in [0021], Figs. 1,2) on the first substrate (110-bottom), and a first insulating layer (164b an insulation layer in [0029], Figs. 1,2) at least partially surrounding (Figs. 1,2) the first pad (154) on the first substrate (110-bottom); and
a second semiconductor chip (100B semiconductor chip in [0021], Figs. 1,2) on the first semiconductor chip (100A), and including a second substrate (110-top a semiconductor substrate in [0021], Figs. 1,2-Annotated), a second pad (152 a connection pad in [0021], Figs. 1,2) below the second substrate (110-top) and contacting (Figs. 1,2) the first pad (154), and a second insulating layer (162 an insulation layer in [0028], Figs. 1,2) at least partially surrounding (Figs. 1,2) the second pad (152) and contacting (Figs. 1,2) the first insulating layer (162),
wherein the first pad (154) includes a first surface (first surface-154 top surface of pad 154, Fig. 2-Annotated) contacting the second pad (152) and a second surface (second surface-154 bottom surface of pad 154, Fig. 2-Annotated) opposite (Fig. 2-Annotated) the first surface (first surface-154).
Hwang does not expressly disclose inclined side surfaces between the first surface and the second surface, wherein the inclined side surfaces include a first side surface and a second side surface, facing each other and inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively, and wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°.
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Watanabe’s Figure 1-Annotated.
However, in the same semiconductor device field of endeavor, Watanabe discloses inclined side surfaces (23-side-L and 23-side-R an inclined side surface of pad 23 at left side and right side, wherein 23 includes 23a metal film and 23b barrier layer in [0060], Fig. 1-Annotated) between the first surface (first surface top surface of pad 23 in [0060], Fig. 1-Annotated) and the second surface (second surface bottom surface of pad 23 in [0060], Fig. 1-Annotated), wherein the inclined side surfaces (23-side-L and 23-side-R Fig. 1-Annotated) include a first side surface (23-side-L, Fig. 1-Annotated) and a second side surface (23-side-R, Fig. 1-Annotated), facing each other (Fig. 1-Annotated) and inclined at a first angle (23-angle-L, an angle formed between the second surface and the inclined surface, Fig. 1-Annotated) and a second angle (23-angle-R, an angle formed between the second surface and the inclined surface, Fig. 1-Annotated) with respect to the second surface (second surface, Fig. 1-Annotated), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of inclined side surfaces between the first surface and the second surface, wherein the inclined side surfaces include a first side surface and a second side surface, facing each other and inclined at a first angle and a second angle with respect to the second surface, respectively to Hwang’s device to improve the electrical properties for reducing a parasitic capacitance ([0067], Watanabe).
Hwang modified by Watanabe does not expressly disclose wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°.
However, in the same semiconductor device field of endeavor, Chang discloses wherein at least one the first (ϴ an angle bottom surface 262 and the side surface 263 of the pad portion 26 in [0047], Fig.2-Annotated) or the second angles are obtuse (angle ϴ is an obtuse angle then include the angle 130° in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chang’s feature of wherein at least one the first or the second angles are obtuse to the combination of Hwang and Watanabe to reduce a whole thickness of the semiconductor package ([0002], Chang).
Still, Hwang modified by Watanabe and Chang does not expressly disclose wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°.
However, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, then, the claimed range of about 100° to 130° lie inside of the Chang’s range of 90° to 180°. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05. (I).
Re: Claim 2, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 1, wherein the second pad (152, Hwang) comprises: a third surface (third surface-152 bottom surface of pad 152, Fig. 2-Annotated, Hwang) contacting the first pad (154, Hwang); a fourth surface (fourth surface-152 top surface of pad 152, Fig. 2-Annotated, Hwang) opposite the third surface (third surface-152, Hwang).
Hwang modified by Watanabe and Chang does not expressly disclose an inclined side surface between the third surface and the fourth surface, wherein the inclined side surface includes a third side surface and a fourth side surface, facing each other and inclined at a third obtuse angle and a fourth obtuse angle with respect to the fourth surface, respectively, and each of the third and fourth obtuse angles are about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Watanabe discloses an inclined side surface (13-side-L and 13-side-R an inclined side surface of pad 13 at left side and right side, wherein 13 includes 13a metal film and 13b barrier layer in [0053], Fig. 1-Annotated) between the third surface (third surface bottom surface of pad 13 in [0053], Fig. 1-Annotated) and the fourth surface (fourth surface top surface of pad 13 in [0053], Fig. 1-Annotated), wherein the inclined side surface (13-side-L and 13-side-R) includes a third side surface (13-side-L an inclined side surface of pad 13 at left side, in [0053], Fig. 1-Annotated) and a fourth side surface (13-side-R an inclined side surface of pad 13 at right side, in [0053], Fig. 1-Annotated), facing each other (Fig. 1-Annotated) and inclined at a third angle (13-angle-L, an angle formed between the surface and the inclined surface, Fig. 1-Annotated) and a fourth angle (13-angle-R, an angle formed between the surface and the inclined surface Fig. 1-Annotated) with respect to the fourth surface (fourth surface Fig. 1-Annotated), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of an inclined side surface between the third surface and the fourth surface, wherein the inclined side surface includes a third side surface and a fourth side surface, facing each other and inclined at a third angle and a fourth angle with respect to the fourth surface, respectively to the combination of Hwang, Watanabe and Chang to improve the electrical properties for reducing a parasitic capacitance ([0067], Watanabe).
Hwang modified by Watanabe and Chang does not expressly disclose wherein each of the third and fourth obtuse angles are about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Chang discloses wherein an angle (ϴ an angle bottom surface 262 and the side surface 263 of the pad portion 26 in [0047], Fig.2-Annotated) of about 100° to about 130° (angle ϴ is an obtuse angle then include the angle 100° to 130° in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chang’s feature of an angle of about 100° to about 130° to obtain wherein each of the third and fourth obtuse angles are about 100° to about 130° to the combination of Hwang, Watanabe and Chang to reduce a whole thickness of the semiconductor package ([0002], Chang).
Re: Claim 3, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 1,
Hwang modified by Watanabe and Chang does not disclose wherein the first and second obtuse angles are different from each other.
However, the Applicant has not presented persuasive evidence that the claimed
“first and second obtuse angles different from each other” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed first and second obtuse angles different from each other). Also, the applicant has not shown that the claimed “difference of the claimed first and second obtuse angles” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Watanabe discloses “first and second angles similar from each other” in Fig. 1, therefore, the obtuse angles are a result effective variable. It has been held that is not inventive to discover the optimum first and second obtuse angles by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add first and second obtuse angles different from each other to the rest of the claimed invention to improve the bonding characteristics of the device.
Re: Claim 4, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 2,
Hwang modified by Watanabe and Chang does not disclose wherein the third and fourth obtuse angles are different from each other.
However, the Applicant has not presented persuasive evidence that the claimed
“third and fourth obtuse angles different from each other” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed third and fourth obtuse angles different from each other). Also, the applicant has not shown that the claimed “difference of the claimed third and fourth obtuse angles” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Watanabe discloses “third and fourth obtuse angles similar from each other” in Fig. 1, therefore, the obtuse angles are a result effective variable. It has been held that is not inventive to discover the optimum third and fourth obtuse angles by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add third and fourth obtuse angles different from each other to the rest of the claimed invention to improve the bonding characteristics of the device.
Re: Claim 5, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 1,
Hwang modified by Watanabe and Chang does not disclose wherein a thickness of the first pad is less than a thickness of the second pad.
However, the Applicant has not presented persuasive evidence that the claimed
“thickness of the first pad less than a thickness of the second pad” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thickness of the first pad less than a thickness of the second pad). Also, the applicant has not shown that the claimed “difference of the claimed thickness of the first pad less than a thickness of the second pad” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Watanabe discloses “thickness of the first pad similar to a thickness of the second pad” in Fig. 1, therefore, the thickness of the first pad and the second pad are a result effective variable. It has been held that is not inventive to discover the optimum thickness of the first pad and the second pad by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the thickness of the first pad less than a thickness of the second pad to the rest of the claimed invention to improve the bonding characteristics of the device.
Re: Claim 11, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 1, wherein the first pad (154, Fig. 2, Hwang) comprises a first conductive layer (154 made of copper in [0026], Fig. 2, Hwang) and a first barrier layer (23b barrier layer from Watanabe applied to 154’s Hwang) surrounding (Fig. 1, Watanabe) a side surface of the first conductive layer (154, Fig. 2, Hwang), and wherein the second pad (152, Fig. 2, Hwang) comprises a second conductive layer (152 made of copper in [0026], Fig. 2, Hwang) contacting (Fig. 2, Hwang) at least a portion of the first conductive layer (154, Fig. 2, Hwang).
Hwang modified by Watanabe and Chang does not expressly disclose a second barrier layer surrounding a side surface of the second conductive layer.
However, in the same semiconductor device field of endeavor, Watanabe discloses a second barrier layer (13b barrier layer in [0052], Fig.1, Watanabe) surrounding a side surface of the second conductive layer (13a metal film in [0053], Fig.1, Watanabe).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of a second barrier layer surrounding a side surface of the second conductive layer to the combination of Hwang, Watanabe and Chang to avoid the metal diffusion in other layers ([0052], Watanabe).
Re: Claim 13, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 1, wherein the first semiconductor chip (100A, Fig. 2, Hwang) further comprises a first circuit layer (120 semiconductor device layer including wiring layers in [0022], Figs. 1, 2, Hwang) below the first substrate (110-bottom, Fig. 2, Hwang), a lower pad (pad-170 a lower pad connected to connection bump 170 in [0039], Fig. 1, Hwang) below the first circuit layer (120, Fig. 2, Hwang), and a first through-electrode (130 through-electrodes in [0023], Figs. 1, 2, Hwang) extending through (Figs. 1, 2, Hwang) the first substrate (110-bottom, Fig. 2, Hwang) and electrically connecting the first pad (154, Fig. 2, Hwang) and the lower pad (pad-170, Fig. 2, Hwang).
Re: Independent Claim 14, Hwang discloses a semiconductor package (Fig. 1) comprising:
a first semiconductor chip (100A semiconductor chip in [0021], Figs. 1,2) including a first substrate (110-bottom a semiconductor substrate in [0021], Figs. 1,2-Annotated), a first pad (154 a bonding pad in [0021], Figs. 1,2) on the first substrate (110-bottom), and a first insulating layer (164b an insulation layer in [0029], Figs. 1,2) at least partially surrounding (Figs. 1,2) the first pad (154) on the first substrate (110-bottom); and
a second semiconductor chip (100B semiconductor chip in [0021], Figs. 1,2) on the first semiconductor chip (100A), and including a second substrate (110-top a semiconductor substrate in [0021], Figs. 1,2-Annotated), a second pad (152 a connection pad in [0021], Figs. 1,2) below the second substrate (110-top) and contacting (Figs. 1,2) the first pad (154), and a second insulating layer (162 an insulation layer in [0028], Figs. 1,2) at least partially surrounding (Figs. 1,2) the second pad (152) and contacting (Figs. 1,2) the first insulating layer (162),
wherein the first pad (154) includes a first surface (first surface-154 top surface of pad 154, Fig. 2-Annotated) contacting the second pad (152) and a second surface (second surface-154 bottom surface of pad 154, Fig. 2-Annotated) opposite (Fig. 2-Annotated) the first surface (first surface-154), and a first side surface (side surface-154, Fig. 2-Annotated) between the first surface (first surface-154) and the second surface (second surface-154), and
the second pad (152) includes a third surface (third surface-152 bottom surface of pad 152, Fig. 2-Annotated) contacting the first pad (154), a fourth surface (fourth surface-152 top surface of pad 152, Fig. 2-Annotated) opposite the third surface (third surface-152), and a second side surface (side surface-152, Fig. 2-Annotated) between the third surface (third surface-152) and the fourth surface (fourth surface-152).
Hwang does not expressly disclose a first side surface inclined with respect to the second surface at a first obtuse angle, and a second side surface inclined with respect to the fourth surface at a second obtuse angle, wherein each of the first and second obtuse angles is about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Watanabe discloses a first side surface inclined (23-side-L an inclined side surface of pad 23 at left side, wherein 23 having a trapezoidal shape, includes 23a metal film and 23b barrier layer in [0060], Fig. 1-Annotated) with respect to the second surface (second surface bottom surface of pad 23 in [0060], Fig. 1-Annotated) at a first angle (23-angle-L, an angle formed between the surface and the inclined surface Fig. 1-Annotated), and a second side surface (13-side-L an inclined side surface of pad 13 at left side, wherein 13 includes 13a metal film and 13b barrier layer in [0053], Fig. 1-Annotated) inclined with respect to the fourth surface (fourth surface top surface of pad 13 in [0053], Fig. 1-Annotated) at a second angle (13-angle-L, an angle formed between the surface and the inclined surface Fig. 1-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of a first side surface inclined with respect to the second surface at a first angle, and a second side surface inclined with respect to the fourth surface at a second angle to Hwang’s device to improve the electrical properties for reducing a parasitic capacitance ([0067], Watanabe).
Hwang modified by Watanabe does not expressly disclose wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°.
However, in the same semiconductor device field of endeavor, Chang discloses wherein at least one the first (ϴ an angle bottom surface 262 and the side surface 263 of the pad portion 26 in [0047], Fig.2-Annotated) or the second angles are obtuse (angle ϴ is an obtuse angle then include the angle 130° in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chang’s feature of wherein at least one the first or the second angles are obtuse to the combination of Hwang and Watanabe to reduce a whole thickness of the semiconductor package ([0002], Chang).
Still, Hwang modified by Watanabe and Chang does not expressly disclose wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°.
However, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, then, the claimed range of about 100° to 130° lie inside of the Chang’s range of 90° to 180°. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05. (I).
Re: Claim 15, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 14, wherein the first pad (154, Fig. 2, Hwang) has a trapezoidal shape (23 with trapezoidal shape from Watanabe applied to 154’s Hwang).
Re: Claim 16, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 14,
Hwang modified by Watanabe and Chang does not disclose wherein the first obtuse angle and the second obtuse angle are different from each other.
However, the Applicant has not presented persuasive evidence that the claimed
“first obtuse angle and the second obtuse angle different from each other” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed first obtuse angle and the second obtuse angle different from each other). Also, the applicant has not shown that the claimed “difference of the claimed first obtuse angle and the second obtuse angle” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Watanabe discloses “first angle and the second angle similar from each other” in Fig. 1, therefore, the obtuse angles are a result effective variable. It has been held that is not inventive to discover the optimum first obtuse angle and the second obtuse angle by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first obtuse angle and the second obtuse angle different from each other to the rest of the claimed invention to improve the bonding characteristics of the device.
Re: Claim 17, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 14, wherein the first semiconductor chip (100A, Fig. 2, Hwang) further comprises a first circuit layer (120 semiconductor device layer including wiring layers in [0022], Figs. 1, 2, Hwang) below the first substrate (110-bottom, Fig. 2, Hwang), a lower pad (pad-170 a lower pad connected to connection bump 170 in [0039], Fig. 1, Hwang) below the first circuit layer (120, Fig. 2, Hwang), and a first through-electrode (130 through-electrodes in [0023], Figs. 1, 2, Hwang) extending through (Figs. 1, 2, Hwang) the first substrate (110-bottom, Fig. 2, Hwang) and electrically connecting the first pad (154, Fig. 2, Hwang) and the lower pad (pad-170, Fig. 2, Hwang).
Re: Claim 21, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 1, wherein the first pad (154, Fig. 2, Hwang) has a trapezoidal shape (23 with trapezoidal shape from Watanabe applied to 154’s Hwang).
Re: Claim 26, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 13, wherein the first through-electrode (130 through-electrodes in [0023], Figs. 1, 2, Hwang) is directly in contact with the second surface (second surface-154 bottom surface of pad 154, Fig. 2-Annotated) of the first pad (154, Fig. 2, Hwang).
Claim(s) 18-19 and 27 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 20200135699 A1, of the record), in view of Mun et al. (US 20230335580 A1, hereinafter Mun, of the record), in view of Watanabe (US 20210280545 A1, hereinafter Watanabe, of the record) and further in view Chang et al. (US 20210210423 A1, hereinafter Chang).
Re: Independent Claim 18, Hwang discloses a semiconductor package (Fig. 1) comprising:
a first semiconductor chip (100A semiconductor chip in [0021], Figs. 1,2) including a first substrate (110-bottom a semiconductor substrate in [0021], Figs. 1,2-Annotated), a first pad (154 a bonding pad in [0021], Figs. 1,2) on the first substrate (110-bottom), and a first insulating layer (164b an insulation layer in [0029], Figs. 1,2) at least partially surrounding (Figs. 1,2) the first pad (154) on the first substrate (110-bottom), an insulating protective layer (164a an insulation layer in [0029], Figs. 1,2) between the first substrate (110-bottom) and the first insulating layer (164b), a through-electrode (130 through-electrode in [0029], Figs. 1,2) extending through the first substrate (110-bottom) and the insulating protective layer (164a) and connected to the first pad (154), and
a second semiconductor chip (100B semiconductor chip in [0021], Figs. 1,2) on the first semiconductor chip (100A), and including a second substrate (110-top a semiconductor substrate in [0021], Figs. 1,2-Annotated), a second pad (152 a connection pad in [0021], Figs. 1,2) below the second substrate (110-top) and contacting (Figs. 1,2) the first pad (154), and a second insulating layer (162 an insulation layer in [0028], Figs. 1,2) at least partially surrounding (Figs. 1,2) the second pad (152) and contacting (Figs. 1,2) the first insulating layer (162),
wherein the first pad (154) includes a first surface (first surface-154 top surface of pad 154, Fig. 2-Annotated) contacting the second pad (152) and a second surface (second surface-154 bottom surface of pad 154, Fig. 2-Annotated) opposite (Fig. 2-Annotated) the first surface (first surface-154);
Hwang does not expressly disclose a buffer film on the insulating protective layer and spaced apart from the through-electrode; wherein the first pad has a first side surface and an opposite second side surface inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively, and wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°.
However, in the same semiconductor device field of endeavor, Mun discloses a buffer film (342 etch stop layer made of SiN in [0042], Fig. 18-Annotated) on the insulating protective layer (302a dielectric material in [0042], Fig. 18) and spaced apart (Fig. 18-Annotated) from the through-electrode (306u interconnect vias in [0044], Fig. 18-Annotated).
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Mun’s Figure 18-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Mun’s feature of a buffer film on the insulating protective layer and spaced apart from the through-electrode to Hwang’s device to form interconnect patterns using an etch stop layer ([0042], Mun).
Hwang modified by Mun does not expressly disclose wherein the first pad has a first side surface and an opposite second side surface inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively, and wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°.
However, in the same semiconductor device field of endeavor, Watanabe discloses wherein the first pad (23-side-L and 23-side-R Fig. 1-Annotated) has a first side surface (23-side-L, Fig. 1-Annotated) and an opposite second side surface (23-side-R, Fig. 1-Annotated), inclined (Fig. 1-Annotated) at a first angle (23-angle-L, Fig. 1-Annotated) and a second angle (23-angle-R, Fig. 1-Annotated) with respect to the second surface (second surface, Fig. 1-Annotated), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of wherein the first pad has a first side surface and an opposite second side surface inclined at a first angle and a second angle with respect to the second surface, respectively to the combination of Hwang and Mun to improve the electrical properties for reducing a parasitic capacitance ([0067], Watanabe).
Hwang modified by Mun and Watanabe does not expressly disclose wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°.
However, in the same semiconductor device field of endeavor, Chang discloses wherein at least one the first (ϴ an angle bottom surface 262 and the side surface 263 of the pad portion 26 in [0047], Fig.2-Annotated) or the second angles are obtuse (angle ϴ is an obtuse angle then include the angle 130° in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Chang’s feature of wherein at least one the first or the second angles are obtuse to the combination of Hwang and Watanabe to reduce a whole thickness of the semiconductor package ([0002], Chang).
Still, Hwang modified by Watanabe and Chang does not expressly disclose wherein at least one the first or the second obtuse angles is about 100° and less than or equal to 130°.
However, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, then, the claimed range of about 100° to 130° lie inside of the Chang’s range of 90° to 180°. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). See MPEP 2144.05. (I).
Re: Claim 19, Hwang modified by Mun, Watanabe and Chang disclose the semiconductor package of claim 18,
Hwang modified by Mun, Watanabe and Chang do not expressly disclose wherein the buffer film is spaced apart from the first pad.
However, in the same semiconductor device field of endeavor, Mun discloses a buffer film (342 etch stop layer made of SiN in [0042], Fig. 18-Annotated) is spaced apart from a first pad (308u upper interconnect metal in [0043], Fig. 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Mun’s feature of wherein the buffer film is spaced apart from the first pad to the combination of Hwang, Mun, Watanabe and Chang to form interconnect patterns using an etch stop layer ([0042], Mun).
Re: Claim 27, Hwang modified by Mun, Watanabe and Chang disclose the semiconductor package of claim 18,
Hwang modified by Mun, Watanabe and Chang does not disclose wherein a thickness of the first pad is less than a thickness of the second pad.
However, the Applicant has not presented persuasive evidence that the claimed
“thickness of the first pad less than a thickness of the second pad” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thickness of the first pad less than a thickness of the second pad). Also, the applicant has not shown that the claimed “difference of the claimed thickness of the first pad less than a thickness of the second pad” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Watanabe discloses “thickness of the first pad similar to a thickness of the second pad” in Fig. 1, therefore, the thickness of the first pad and the second pad are a result effective variable. It has been held that is not inventive to discover the optimum thickness of the first pad and the second pad by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the thickness of the first pad less than a thickness of the second pad to the rest of the claimed invention to improve the bonding characteristics of the device.
Claim(s) 22-25 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang, in view of Watanabe, in view of Chang and further in view of Mun et al. (US 20230335580 A1, hereinafter Mun).
Re: Claim 22, Hwang modified by Watanabe and Chang discloses the semiconductor package of claim 1,
Hwang modified by Watanabe and Chang do not expressly disclose wherein the first semiconductor chip further includes a buffer film disposed between the first substrate and the first insulating layer, and the buffer film is spaced apart from the first pad and overlaps with at least a portion of the first pad.
However, in the same semiconductor device field of endeavor, Mun discloses a buffer film (342 etch stop layer made of SiN in [0042], Fig. 18-Annotated) disposed between a dielectric layer (136 molding material in [0026], Fig. 18) and the first insulating layer (302c dielectric material in [0045], Fig. 18), and the buffer film (342) is spaced apart (Fig. 18-Annotated) from the first pad (308u upper interconnect metals in [0025], Fig. 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Mun’s feature of a buffer film disposed between the first substrate and the first insulating layer, and the buffer film is spaced apart from the first pad to Hwang’s device to obtain a buffer film disposed between the first substrate and the first insulating layer to form interconnect patterns using an etch stop layer ([0042], Mun).
Hwang modified by Watanabe, Chang and Mun do not expressly disclose wherein the buffer film overlaps with at least a portion of the first pad.
However, the Applicant has not presented persuasive evidence that the claimed size of the buffer film wherein “the buffer film overlaps with at least a portion of the first pad” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed relation of the size between the buffer film and the first pad). Also, the applicant has not shown that the claimed “difference of the buffer film overlaps with at least a portion of the first pad” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Therefore it is a prima facie obvious in view of In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device, see 2144.04 IV(A).
Re: Claim 23, Hwang modified by Watanabe, Chang and Mun discloses the semiconductor package of claim 22, wherein the first semiconductor chip (100A semiconductor chip in [0021], Figs. 1,2, Hwang) further includes an insulating protective layer (164a an insulation layer in [0029], Figs. 1,2, Hwang) between the first substrate (110-bottom, Figs. 1,2, Hwang) and the buffer film (342, Fig. 18-Annotated, Mun), and at least a portion of the insulating protective layer (154 Figs. 1,2, Hwang) is in contact with the second surface of the first pad (164a Figs. 1,2, Hwang).
Re: Claim 24, Hwang modified by Watanabe, Chang and Mun discloses the semiconductor package of claim 23, wherein the first semiconductor chip (100A, Figs. 1,2, Hwang) further includes a through-electrode (130 through-electrodes in [0023], Figs. 1, 2, Hwang) extending through (Figs. 1, 2, Hwang) the first substrate (110-bottom, Figs. 1,2, Hwang) and the insulating protective layer (154 Figs. 1,2, Hwang) and connected to the first pad (164a Figs. 1,2, Hwang), and the through-electrode (130 Figs. 1, 2, Hwang) is spaced apart from the buffer film (342, Fig. 18-Annotated, Mun).
Re: Claim 25, Hwang modified by Watanabe, Chang and Mun discloses the semiconductor package of claim 22,
Hwang modified by Watanabe, Chang and Mun do not expressly disclose wherein an upper surface of the buffer film is at a same level as the second surface of the first pad.
However, the Applicant has not presented persuasive evidence that the claimed distance between an upper surface of the buffer film and the second surface of the first pad, wherein
“an upper surface of the buffer film is at a same level as the second surface of the first pad” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range of the distance between an upper surface of the buffer film and the second surface of the first pad). Also, the applicant has not shown that the claimed “difference of an upper surface of the buffer film and the second surface of the first pad” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Mun discloses “a separation distance between an upper surface of the buffer film (342) and the second surface of the first pad (308u)”, therefore, the distance is a result effective variable. It has been held that is not inventive to discover the optimum distance between an upper surface of the buffer film and the second surface of the first pad by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an upper surface of the buffer film is at a same level as the second surface of the first pad to the rest of the claimed invention to tune the design of the device according to desired characteristics.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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