DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species (a), (claims 1-5, 11 and 13-19), in the reply filed
on 12/18/2025 is acknowledged. Non-elected claims 6-10, 12 and 20 are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 18, it recites the limitation “…an inclined side surface between the first surface and the second surface, wherein the first pad has a first side surface and an opposite second side surface…” is not explained. The limitation has an antecedent issue of “a first side surface” and “an opposite second side surface”. Therefore, it is indefinite, it appears that the inclined side surface includes a first side surface and an opposite second side surface. For the examination purpose and according to Fig. 1B, the limitation “…an inclined side surface between the first surface and the second surface, wherein the first pad has a first side surface and an opposite second side surface…” is interpreted as “…and inclined side surfaces between the first surface and second surface, wherein the inclined side surfaces include a first side surface and an opposite second side surface…”.
Regarding claim 19, this is rejected under 35 U.S.C. 112 (b), because of their dependency status from claim 18.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 11 and 13-17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 20200135699 A1) in view of Watanabe (US 20210280545 A1, hereinafter Watanabe) and further in view of Lee (US 20180315620 A1, hereinafter Lee).
Re: Independent Claim 1, Hwang discloses a semiconductor package (Fig. 1) comprising:
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Hwang’s Figure 2-Annotated.
a first semiconductor chip (100A semiconductor chip in [0021], Figs. 1,2) including a first substrate (110-bottom a semiconductor substrate in [0021], Figs. 1,2-Annotated), a first pad (154 a bonding pad in [0021], Figs. 1,2) on the first substrate (110-bottom), and a first insulating layer (164b an insulation layer in [0029], Figs. 1,2) at least partially surrounding (Figs. 1,2) the first pad (154) on the first substrate (110-bottom); and
a second semiconductor chip (100B semiconductor chip in [0021], Figs. 1,2) on the first semiconductor chip (100A), and including a second substrate (110-top a semiconductor substrate in [0021], Figs. 1,2-Annotated), a second pad (152 a connection pad in [0021], Figs. 1,2) below the second substrate (110-top) and contacting (Figs. 1,2) the first pad (154), and a second insulating layer (162 an insulation layer in [0028], Figs. 1,2) at least partially surrounding (Figs. 1,2) the second pad (152) and contacting (Figs. 1,2) the first insulating layer (162),
wherein the first pad (154) includes a first surface (first surface-154 top surface of pad 154, Fig. 2-Annotated) contacting the second pad (152) and a second surface (second surface-154 bottom surface of pad 154, Fig. 2-Annotated) opposite (Fig. 2-Annotated) the first surface (first surface-154).
Hwang does not expressly disclose an inclined side surface between the first surface and the second surface, wherein the inclined side surface includes a first side surface and a second side surface, facing each other and inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively, and wherein each of the first and second obtuse angles is about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Watanabe discloses an inclined side surface (23-side-L and 23-side-R an inclined side surface of pad 23 at left side and right side, wherein 23 includes 23a metal film and 23b barrier layer in [0060], Fig. 1-Annotated) between the first surface (first surface top surface of pad 23 in [0060], Fig. 1-Annotated) and the second surface (second surface bottom surface of pad 23 in [0060], Fig. 1-Annotated), wherein the inclined side surface (23-side-L and 23-side-R Fig. 1-Annotated) includes a first side surface (23-side-L, Fig. 1-Annotated) and a second side surface (23-side-R, Fig. 1-Annotated), facing each other (Fig. 1-Annotated) and inclined at a first obtuse angle (23-angle-L, an inclination greater than 90° and less than 180° Fig. 1-Annotated) and a second obtuse angle (23-angle-R, an inclination greater than 90° and less than 180° Fig. 1-Annotated) with respect to the second surface (second surface, Fig. 1-Annotated), respectively.
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Watanabe’s Figure 1-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of an inclined side surface between the first surface and the second surface, wherein the inclined side surface includes a first side surface and a second side surface, facing each other and inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively to Hwang’s device to improve the electrical properties for reducing a parasitic capacitance ([0067], Watanabe).
Hwang modified by Watanabe does not expressly disclose wherein each of the first and second obtuse angles is about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Lee discloses a first (ϴ1-L an angle bottom surface 300b and the sidewall 300c of the pad structure 300 at left side in [0035], Fig.2B-Annotated) and second obtuse angles (ϴ1-R an angle bottom surface 300b and the sidewall 300c of the pad structure 300 at right side in [0035], Fig.2B-Annotated) is about 100° to about 130° (angles ϴ1 are equal to 120 degrees in [0035]).
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Lee’s Figure 2B-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lee’s feature of wherein each of the first and second obtuse angles is about 100° to about 130° to the combination of Hwang and Watanabe to reduce stress in the pad structure ([0035], Lee).
Re: Claim 2, Hwang modified by Watanabe and Lee discloses the semiconductor package of claim 1, wherein the second pad (152, Hwang) comprises: a third surface (third surface-152 bottom surface of pad 152, Fig. 2-Annotated, Hwang) contacting the first pad (154, Hwang); a fourth surface (fourth surface-152 top surface of pad 152, Fig. 2-Annotated, Hwang) opposite the third surface (third surface-152, Hwang).
Hwang modified by Watanabe and Lee does not expressly disclose an inclined side surface between the third surface and the fourth surface, wherein the inclined side surface includes a third side surface and a fourth side surface, facing each other and inclined at a third obtuse angle and a fourth obtuse angle with respect to the fourth surface, respectively, and each of the third and fourth obtuse angles are about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Watanabe discloses an inclined side surface (13-side-L and 13-side-R an inclined side surface of pad 13 at left side and right side, wherein 13 includes 13a metal film and 13b barrier layer in [0053], Fig. 1-Annotated) between the third surface (third surface bottom surface of pad 13 in [0053], Fig. 1-Annotated) and the fourth surface (fourth surface top surface of pad 13 in [0053], Fig. 1-Annotated), wherein the inclined side surface (13-side-L and 13-side-R) includes a third side surface (13-side-L an inclined side surface of pad 13 at left side, in [0053], Fig. 1-Annotated) and a fourth side surface (13-side-R an inclined side surface of pad 13 at right side, in [0053], Fig. 1-Annotated), facing each other (Fig. 1-Annotated) and inclined at a third obtuse angle (13-angle-L, an inclination greater than 90° and less than 180° Fig. 1-Annotated) and a fourth obtuse angle (13-angle-R, an inclination greater than 90° and less than 180° Fig. 1-Annotated) with respect to the fourth surface (fourth surface Fig. 1-Annotated), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of an inclined side surface between the third surface and the fourth surface, wherein the inclined side surface includes a third side surface and a fourth side surface, facing each other and inclined at a third obtuse angle and a fourth obtuse angle with respect to the fourth surface, respectively to the combination of Hwang, Watanabe and Lee to improve the electrical properties for reducing a parasitic capacitance ([0067], Watanabe).
Hwang modified by Watanabe and Lee does not expressly disclose wherein each of the third and fourth obtuse angles are about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Lee discloses a third (ϴ1-L an angle bottom surface 300b and the sidewall 300c of the pad structure 300 at left side in [0035], Fig.2B-Annotated) and fourth obtuse angles (ϴ1-R an angle bottom surface 300b and the sidewall 300c of the pad structure 300 at right side in [0035], Fig.2B-Annotated) are about 100° to about 130° (angles ϴ1 are equal to 120 degrees in [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lee’s feature of wherein each of the third and fourth obtuse angles are about 100° to about 130° to the combination of Hwang, Watanabe and Lee to reduce stress in the pad structure ([0035], Lee).
Re: Claim 3, Hwang modified by Watanabe and Lee discloses the semiconductor package of claim 1,
Hwang modified by Watanabe and Lee does not disclose wherein the first and second obtuse angles are different from each other.
However, the Applicant has not presented persuasive evidence that the claimed
“first and second obtuse angles different from each other” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed first and second obtuse angles different from each other). Also, the applicant has not shown that the claimed “difference of the claimed first and second obtuse angles” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Watanabe discloses “first and second obtuse angles similar from each other” in Fig. 1, therefore, the obtuse angles are a result effective variable. It has been held that is not inventive to discover the optimum first and second obtuse angles by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add first and second obtuse angles different from each other to the rest of the claimed invention to improve the bonding characteristics of the device.
Re: Claim 4, Hwang modified by Watanabe and Lee discloses the semiconductor package of claim 2,
Hwang modified by Watanabe and Lee does not disclose wherein the third and fourth obtuse angles are different from each other.
However, the Applicant has not presented persuasive evidence that the claimed
“third and fourth obtuse angles different from each other” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed third and fourth obtuse angles different from each other). Also, the applicant has not shown that the claimed “difference of the claimed third and fourth obtuse angles” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Watanabe discloses “third and fourth obtuse angles similar from each other” in Fig. 1, therefore, the obtuse angles are a result effective variable. It has been held that is not inventive to discover the optimum third and fourth obtuse angles by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add third and fourth obtuse angles different from each other to the rest of the claimed invention to improve the bonding characteristics of the device.
Re: Claim 5, Hwang modified by Watanabe and Lee discloses the semiconductor package of claim 1,
Hwang modified by Watanabe and Lee does not disclose wherein a thickness of the first pad is less than a thickness of the second pad.
However, the Applicant has not presented persuasive evidence that the claimed
“thickness of the first pad less than a thickness of the second pad” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thickness of the first pad less than a thickness of the second pad). Also, the applicant has not shown that the claimed “difference of the claimed thickness of the first pad less than a thickness of the second pad” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Watanabe discloses “thickness of the first pad similar to a thickness of the second pad” in Fig. 1, therefore, the thickness of the first pad and the second pad are a result effective variable. It has been held that is not inventive to discover the optimum thickness of the first pad and the second pad by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the thickness of the first pad less than a thickness of the second pad to the rest of the claimed invention to improve the bonding characteristics of the device.
Re: Claim 11, Hwang modified by Watanabe and Lee discloses the semiconductor package of claim 1, wherein the first pad (154, Fig. 2, Hwang) comprises a first conductive layer (154 made of copper in [0026], Fig. 2, Hwang) and a first barrier layer (23b barrier layer from Watanabe applied to 154’s Hwang) surrounding (Fig. 1, Watanabe) a side surface of the first conductive layer (154, Fig. 2, Hwang), and wherein the second pad (152, Fig. 2, Hwang) comprises a second conductive layer (152 made of copper in [0026], Fig. 2, Hwang) contacting (Fig. 2, Hwang) at least a portion of the first conductive layer (154, Fig. 2, Hwang).
Hwang modified by Watanabe and Lee does not expressly disclose a second barrier layer surrounding a side surface of the second conductive layer.
However, in the same semiconductor device field of endeavor, Watanabe discloses a second barrier layer (13b barrier layer in [0052], Fig.1, Watanabe) surrounding a side surface of the second conductive layer (13a metal film in [0053], Fig.1, Watanabe).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of a second barrier layer surrounding a side surface of the second conductive layer to the combination of Hwang, Watanabe and Lee to avoid the metal diffusion in other layers ([0052], Watanabe).
Re: Claim 13, Hwang modified by Watanabe and Lee discloses the semiconductor package of claim 1, wherein the first semiconductor chip (100A, Fig. 2, Hwang) further comprises a first circuit layer (120 semiconductor device layer including wiring layers in [0022], Figs. 1, 2, Hwang) below the first substrate (110-bottom, Fig. 2, Hwang), a lower pad (pad-170 a lower pad connected to connection bump 170 in [0039], Fig. 1, Hwang) below the first circuit layer (120, Fig. 2, Hwang), and a first through-electrode (130 through-electrodes in [0023], Figs. 1, 2, Hwang) extending through (Figs. 1, 2, Hwang) the first substrate (110-bottom, Fig. 2, Hwang) and electrically connecting the first pad (154, Fig. 2, Hwang) and the lower pad (pad-170, Fig. 2, Hwang).
Re: Independent Claim 14, Hwang discloses a semiconductor package (Fig. 1) comprising:
a first semiconductor chip (100A semiconductor chip in [0021], Figs. 1,2) including a first substrate (110-bottom a semiconductor substrate in [0021], Figs. 1,2-Annotated), a first pad (154 a bonding pad in [0021], Figs. 1,2) on the first substrate (110-bottom), and a first insulating layer (164b an insulation layer in [0029], Figs. 1,2) at least partially surrounding (Figs. 1,2) the first pad (154) on the first substrate (110-bottom); and
a second semiconductor chip (100B semiconductor chip in [0021], Figs. 1,2) on the first semiconductor chip (100A), and including a second substrate (110-top a semiconductor substrate in [0021], Figs. 1,2-Annotated), a second pad (152 a connection pad in [0021], Figs. 1,2) below the second substrate (110-top) and contacting (Figs. 1,2) the first pad (154), and a second insulating layer (162 an insulation layer in [0028], Figs. 1,2) at least partially surrounding (Figs. 1,2) the second pad (152) and contacting (Figs. 1,2) the first insulating layer (162),
wherein the first pad (154) includes a first surface (first surface-154 top surface of pad 154, Fig. 2-Annotated) contacting the second pad (152) and a second surface (second surface-154 bottom surface of pad 154, Fig. 2-Annotated) opposite (Fig. 2-Annotated) the first surface (first surface-154), and a first side surface (side surface-154, Fig. 2-Annotated) between the first surface (first surface-154) and the second surface (second surface-154), and
the second pad (152) includes a third surface (third surface-152 bottom surface of pad 152, Fig. 2-Annotated) contacting the first pad (154), a fourth surface (fourth surface-152 top surface of pad 152, Fig. 2-Annotated) opposite the third surface (third surface-152), and a second side surface (side surface-152, Fig. 2-Annotated) between the third surface (third surface-152) and the fourth surface (fourth surface-152).
Hwang does not expressly disclose a first side surface inclined with respect to the second surface at a first obtuse angle, and a second side surface inclined with respect to the fourth surface at a second obtuse angle, wherein each of the first and second obtuse angles is about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Watanabe discloses a first side surface inclined (23-side-L an inclined side surface of pad 23 at left side, wherein 23 having a trapezoidal shape, includes 23a metal film and 23b barrier layer in [0060], Fig. 1-Annotated) with respect to the second surface (second surface bottom surface of pad 23 in [0060], Fig. 1-Annotated) at a first obtuse angle (23-angle-L, an inclination greater than 90° and less than 180° Fig. 1-Annotated), and a second side surface (13-side-L an inclined side surface of pad 13 at left side, wherein 13 includes 13a metal film and 13b barrier layer in [0053], Fig. 1-Annotated) inclined with respect to the fourth surface (fourth surface top surface of pad 13 in [0053], Fig. 1-Annotated) at a second obtuse angle (13-angle-L, an inclination greater than 90° and less than 180° Fig. 1-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of a first side surface inclined with respect to the second surface at a first obtuse angle, and a second side surface inclined with respect to the fourth surface at a second obtuse angle to Hwang’s device to improve the electrical properties for reducing a parasitic capacitance ([0067], Watanabe).
Hwang modified by Watanabe does not expressly disclose wherein each of the first and second obtuse angles is about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Lee discloses a first (ϴ1-L an angle bottom surface 300b and the sidewall 300c of the pad structure 300 at left side in [0035], Fig.2B-Annotated) and second obtuse angles (ϴ1-R an angle bottom surface 300b and the sidewall 300c of the pad structure 300 at right side in [0035], Fig.2B-Annotated) is about 100° to about 130° (angles ϴ1 are equal to 120 degrees in [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lee’s feature of wherein each of the first and second obtuse angles is about 100° to about 130° to the combination of Hwang and Watanabe to reduce stress in the pad structure ([0035], Lee).
Re: Claim 15, Hwang modified by Watanabe and Lee discloses the semiconductor package of claim 14, wherein the first pad (154, Fig. 2, Hwang) has a trapezoidal shape (23 with trapezoidal shape from Watanabe applied to 154’s Hwang).
Re: Claim 16, Hwang modified by Watanabe and Lee discloses the semiconductor package of claim 14,
Hwang modified by Watanabe and Lee does not disclose wherein the first obtuse angle and the second obtuse angle are different from each other.
However, the Applicant has not presented persuasive evidence that the claimed
“first obtuse angle and the second obtuse angle different from each other” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed first obtuse angle and the second obtuse angle different from each other). Also, the applicant has not shown that the claimed “difference of the claimed first obtuse angle and the second obtuse angle” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Watanabe discloses “first obtuse angle and the second obtuse angle similar from each other” in Fig. 1, therefore, the obtuse angles are a result effective variable. It has been held that is not inventive to discover the optimum first obtuse angle and the second obtuse angle by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first obtuse angle and the second obtuse angle different from each other to the rest of the claimed invention to improve the bonding characteristics of the device.
Re: Claim 17, Hwang modified by Watanabe and Lee discloses the semiconductor package of claim 14, wherein the first semiconductor chip (100A, Fig. 2, Hwang) further comprises a first circuit layer (120 semiconductor device layer including wiring layers in [0022], Figs. 1, 2, Hwang) below the first substrate (110-bottom, Fig. 2, Hwang), a lower pad (pad-170 a lower pad connected to connection bump 170 in [0039], Fig. 1, Hwang) below the first circuit layer (120, Fig. 2, Hwang), and a first through-electrode (130 through-electrodes in [0023], Figs. 1, 2, Hwang) extending through (Figs. 1, 2, Hwang) the first substrate (110-bottom, Fig. 2, Hwang) and electrically connecting the first pad (154, Fig. 2, Hwang) and the lower pad (pad-170, Fig. 2, Hwang).
Claim(s) 18-19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 20200135699 A1), in view of Mun et al. (US 20230335580 A1, hereinafter Mun), in view of Watanabe (US 20210280545 A1, hereinafter Watanabe) and further in view of Lee (US 20180315620 A1, hereinafter Lee).
Re: Independent Claim 18, Hwang discloses a semiconductor package (Fig. 1) comprising:
a first semiconductor chip (100A semiconductor chip in [0021], Figs. 1,2) including a first substrate (110-bottom a semiconductor substrate in [0021], Figs. 1,2-Annotated), a first pad (154 a bonding pad in [0021], Figs. 1,2) on the first substrate (110-bottom), and a first insulating layer (164b an insulation layer in [0029], Figs. 1,2) at least partially surrounding (Figs. 1,2) the first pad (154) on the first substrate (110-bottom), an insulating protective layer (164a an insulation layer in [0029], Figs. 1,2) between the first substrate (110-bottom) and the first insulating layer (164b), a through-electrode (130 through-electrode in [0029], Figs. 1,2) extending through the first substrate (110-bottom) and the insulating protective layer (164a) and connected to the first pad (154), and
a second semiconductor chip (100B semiconductor chip in [0021], Figs. 1,2) on the first semiconductor chip (100A), and including a second substrate (110-top a semiconductor substrate in [0021], Figs. 1,2-Annotated), a second pad (152 a connection pad in [0021], Figs. 1,2) below the second substrate (110-top) and contacting (Figs. 1,2) the first pad (154), and a second insulating layer (162 an insulation layer in [0028], Figs. 1,2) at least partially surrounding (Figs. 1,2) the second pad (152) and contacting (Figs. 1,2) the first insulating layer (162),
wherein the first pad (154) includes a first surface (first surface-154 top surface of pad 154, Fig. 2-Annotated) contacting the second pad (152) and a second surface (second surface-154 bottom surface of pad 154, Fig. 2-Annotated) opposite (Fig. 2-Annotated) the first surface (first surface-154);
Hwang does not expressly disclose a buffer film on the insulating protective layer and spaced apart from the through-electrode; an inclined side surface between the first surface and the second surface, wherein the inclined side surfaces include a first side surface and an opposite second side surface inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively, and wherein each of the first and second obtuse angles is about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Mun discloses a buffer film (342 etch stop layer made of SiN in [0042], Fig. 18-Annotated) on the insulating protective layer (302a dielectric material in [0042], Fig. 18) and spaced apart (Fig. 18-Annotated) from the through-electrode (306u interconnect vias in [0044], Fig. 18-Annotated).
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Mun’s Figure 18-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Mun’s feature of a buffer film on the insulating protective layer and spaced apart from the through-electrode to Hwang’s device to form interconnect patterns using an etch stop layer ([0042], Mun).
Hwang modified by Mun does not expressly disclose an inclined side surface between the first surface and the second surface, wherein the inclined side surfaces include a first side surface and an opposite second side surface inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively, and wherein each of the first and second obtuse angles is about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Watanabe discloses an inclined side surface (23-side-L and 23-side-R an inclined side surface of pad 23 at left side and right side, wherein 23 includes 23a metal film and 23b barrier layer in [0060], Fig. 1-Annotated) between the first surface (first surface top surface of pad 23 in [0060], Fig. 1-Annotated) and the second surface (second surface bottom surface of pad 23 in [0060], Fig. 1-Annotated), wherein the inclined side surfaces (23-side-L and 23-side-R Fig. 1-Annotated) include a first side surface (23-side-L, Fig. 1-Annotated) and an opposite second side surface (23-side-R, Fig. 1-Annotated), inclined (Fig. 1-Annotated) at a first obtuse angle (23-angle-L, an inclination greater than 90° and less than 180° Fig. 1-Annotated) and a second obtuse angle (23-angle-R, an inclination greater than 90° and less than 180° Fig. 1-Annotated) with respect to the second surface (second surface, Fig. 1-Annotated), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Watanabe’s feature of an inclined side surface between the first surface and the second surface, wherein the inclined side surfaces include a first side surface and an opposite second side surface inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively to the combination of Hwang and Mun to improve the electrical properties for reducing a parasitic capacitance ([0067], Watanabe).
Hwang modified by Mun and Watanabe does not expressly disclose wherein each of the first and second obtuse angles is about 100° to about 130°.
However, in the same semiconductor device field of endeavor, Lee discloses a first (ϴ1-L an angle bottom surface 300b and the sidewall 300c of the pad structure 300 at left side in [0035], Fig.2B-Annotated) and second obtuse angles (ϴ1-R an angle bottom surface 300b and the sidewall 300c of the pad structure 300 at right side in [0035], Fig.2B-Annotated) is about 100° to about 130° (angles ϴ1 are equal to 120 degrees in [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Lee’s feature of wherein each of the first and second obtuse angles is about 100° to about 130° to the combination of Hwang, Mun and Watanabe to reduce stress in the pad structure ([0035], Lee).
Re: Claim 19, Hwang modified by Mun, Watanabe and Lee disclose the semiconductor package of claim 18,
Hwang modified by Mun, Watanabe and Lee do not expressly disclose wherein the buffer film is spaced apart from the first pad.
However, in the same semiconductor device field of endeavor, Mun discloses a buffer film (342 etch stop layer made of SiN in [0042], Fig. 18-Annotated) is spaced apart from a first pad (308u upper interconnect metal in [0043], Fig. 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Mun’s feature of wherein the buffer film is spaced apart from the first pad to the combination of Hwang, Mun, Watanabe and Lee to form interconnect patterns using an etch stop layer ([0042], Mun).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee (US 20200161277 A1) teaches “SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME”. This document is related to a semiconductor package including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.
Chen (US 10854574 B2) teaches “FORMING METAL BONDS WITH RECESSES”. This document is related to a semiconductor device including a first device die, which includes a first dielectric layer, and a first metal pad in the first dielectric layer. The first metal pad includes a recess. The device further includes a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898