Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 25, 2023, March 1, 2024, May 9, 2024, November 24, 2025, January 21, 2026, May 5, 2026, June 16, 2026 is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-14) in the reply filed on May 22, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 3 recites the limitation “each layer” it is unclear if this refers to the insulating layers, the electrically conductive layers or both. For purposes of examination this will be interpreted as “each of the insulating layers and the electrically conductive layers”
Claim 3, line 2 recites the limitation “an alternating stack” it is unclear if this meant to be the alternating stack defined in claim 1 or a different alternating stack. For purposes of examination this will be interpreted as “the alternating stack”
Claim 14 recites the limitation "the same word line switching transistor" in line 5. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “a same word line switching transistor”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pachamuthu (US 2015/0236038).
Claim 1, Pachamuthu discloses (Fig. 21) a memory device, comprising: an alternating stack (132/146 and 232/246, first and second stack, Para [0116]) of insulating layers (132/232, first/second electrically insulating layers, Para [0089]) and electrically conductive layers (146/246, first/second electrically conductive layer, Para [0109]); a memory opening (opening where 50/60 are formed, hereinafter “opening”) vertically extending at least through each of the insulating layers and the electrically conductive layers within the alternating stack (opening extends through 132/232 and 146/246); a memory opening fill structure (50/60, memory film/semiconductor channel, Para [0120]) located in the memory opening (50/60 is located in opening) and comprising a vertical stack of memory elements (50, memory film, Para [0120]) and a vertical semiconductor channel (60, semiconductor channel, Para [0120]); and a bundled contact via structure (174/176, lower-level insulating spacer/ lower-level backside contact trench fill structure, Para [0136]-[0137]) vertically extending through a plurality of bottommost electrically conductive layers of the electrically conductive layers (174/176 extends through 146), and laterally contacting each of the plurality of the bottommost electrically conductive layers (174 of 174/176 laterally contacts each 146). Claim 2, Pachamuthu discloses (Fig. 21) the memory device of Claim 1, wherein the bundled contact via structure (174/176) comprises a straight sidewall that vertically extends from a bottom surface of the bundled contact via structure to a top surface of the bundled contact via structure (174 has left and right sidewalls that extend from a bottom surface of 174 to a top surface of 174).
Allowable Subject Matter
Claims 3-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Pachamuthu (US 2015/0236038), Sano (US Pat. No. 9,601,502), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 3 (from which claims 4-13 depend), the bundled contact via structure vertically extends through the first stepped dielectric material portion.
Regarding Claim 14, the bundled contact via structure electrically connects the bottom source-select gate electrodes to a same word line switching transistor of a peripheral circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sano (US Pat. No. 9,601,502) discloses (Fig. 48) stack 32/46, memory opening fill structure 55, bundled contact via structure 66. Sano does not disclose the bundled contact via structure laterally contacting a plurality of bottommost electrically conductive layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
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