DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8, 10-13 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kajiwara et al. US 2022/0045202 A1.
Regarding claims 1-4, 8 and 10-12, Kajiwara discloses:
A semiconductor device (Figs. 3 and 4), comprising:
a first semiconductor layer (10, para 0020) including a nitride semiconductor;
a second semiconductor layer (20; para 0023) located on the first semiconductor layer, the second semiconductor layer including a nitride semiconductor;
a first electrode (52) located on the second semiconductor layer, the first electrode including
an electrode part (52b) contacting the second semiconductor layer, and
an electrode extension part (52a) extending from an upper end portion of the electrode part in a second direction perpendicular to a first direction, the first direction being from the first semiconductor layer toward the second semiconductor layer;
a second electrode (51) located on the second semiconductor layer, the second electrode being separated from the first electrode in the second direction;
a conductive part (22b; para 0056; ceramic metal nitride … at least thermally conductive) positioned between the first electrode and the second electrode, the conductive part contacting an upper surface of the second semiconductor layer and contacting the first electrode, a length along the second direction from the electrode part to an end portion of the conductive part at the second electrode side (52b inside edge to edge of 22b) being greater than a length along the second direction from the electrode part to an end portion of the electrode extension part at the second electrode side (52b inside edge to end of 52a);
an insulating part (41e) located on the conductive part and positioned between the conductive part and the electrode extension part; and
a third electrode positioned (53) above the second semiconductor layer with an insulating film part (41c) interposed, the third electrode being positioned between the first electrode and the second electrode.
(claim 2) Figs. 3 and 4.
(claim 3) Figs. 3 and 4; a first wiring (62); a first wiring part (62 base); a first wiring extension part (62e).
(claim 4) Figs. 3 and 4; a second wiring (61); a second wiring part (61 base); a second wiring extension part (61e).
(claim 8) Figs. 3 and 4; a plurality of the first electrodes (unnumbered electrode above 52 and 62).
(claim 10) Figs. 3 and 4.
(claim 11) a material of the conductive part (para 0056); material of the first electrode (para 0084).
(claim 12) a first insulating film (41); a second insulating film (43); a third insulating film (44).
Regarding claim 13, Kajiwara discloses:
A method for manufacturing a semiconductor device (Figs. 3, 4, 7 and 8), the method comprising:
forming a conductive part (22b) on a portion of a second semiconductor layer (20), the second semiconductor layer being located on a first semiconductor layer (10), the first semiconductor layer including a nitride semiconductor (para 0020), the second semiconductor layer including a nitride semiconductor (para 0022);
forming an insulating part (41) on a first portion of the conductive part;
forming a first electrode (52), the first electrode including
an electrode part (52b) positioned on the second semiconductor layer, the electrode part contacting the second semiconductor layer and the conductive part, and
an electrode extension part (52a) positioned on the insulating part, the electrode extension part extending in a second direction from an upper end of the electrode part, the second direction being perpendicular to a first direction, the first direction being from the first semiconductor layer toward the second semiconductor layer;
forming a second electrode (51) separated from the first electrode and the conductive part in the second direction, a length along the second direction from the electrode part to an end portion of the conductive part at the second electrode side (52b inside edge to edge of 22b) being greater than a length along the second direction from the electrode part to an end portion of the electrode extension part at the second electrode side (52b inside edge to end of 52a); and
forming a third electrode (53) positioned above the second semiconductor layer with an insulating film part (41c) interposed, the third electrode being positioned between the first electrode and the second electrode.
Regarding claim 15, Kajiwara discloses:
wherein the forming of the insulating part includes:
forming an insulating film on the second semiconductor layer (41) and the conductive part so that the insulating film covers the conductive part (Fig. 8B); and
forming an opening (where 52 is displaced) in the insulating film by removing a portion of the insulating film (Fig. 8D), and
the forming of the first electrode (52) includes forming a portion of the electrode part in the opening (Fig. 8D).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7, 9 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajiwara et al. US 2022/0045202 A1.
Regarding claims 5 and 6, Kajiwara discloses:
further comprising: a second wiring layer (61) located on the second electrode,
the second wiring electrode including
a second wiring part (61 base); and
a second wiring extension part (61e) extending from an upper end portion of the second wiring part toward the first electrode side (Figs. 3 and 4).
Although Kajiwara does not specifically disclose “(claim 5) a length along the second direction between the end portion of the conductive part at the second electrode side and an end portion of the second wiring extension part at the first electrode side being greater than a difference between the length along the second direction from the electrode part to the end portion of the conductive part at the second electrode side and the length along the second direction from the electrode part to the end portion of the electrode extension part at the second electrode side” and “(claim 6) a length along the second direction between the end portion of the conductive part at the second electrode side and an end portion of the second wiring extension part at the first electrode side being greater than a difference between the length along the second direction from the electrode part to the end portion of the conductive part at the second electrode side and the length along the second direction from the electrode part to the end portion of the first wiring extension part at the second electrode side“, Kajiwara does give evidence, in paras 0059-0063, the arrangement of the conductive members 61 and 62 play a critical role in suppressing the concentration of the electric field thereby allowing more stable electrical characteristics in the device. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand based on Kajiwara’s disclosure that such arrangements would be particularly evident in reducing carrier collapse by reducing field crowding in the region underlying the conductive part 22b, where the trapped carriers are able to be discharged to the overlying first electrode achieving the goal of suppressing on-resistance of the device.
Regarding claim 7, although Kajiwara does not specifically disclose “wherein a plurality of the first electrodes is provided, a plurality of the conductive parts is provided, and the plurality of conductive parts respectively contacts the plurality of first electrodes”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to realize the plurality of Kajiwara’s disclosed elements since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 9, although Kajiwara does not specifically disclose “wherein a length of the conductive part in a third direction is greater than a length in the third direction of the electrode extension part, the third direction is perpendicular to the first direction and perpendicular to the second direction, and an end portion in the third direction of the electrode extension part is at a position at which the end portion in the third direction of the electrode extension part overlaps the conductive part in the first direction“, Kajiwara does give evidence, in paras 0059-0063, the arrangement of the electrode and its extension part 52a play a critical role in suppressing the concentration of the electric field thereby allowing more stable electrical characteristics in the device. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand based on Kajiwara’s disclosure that overlapping of the electrode extension part 52a within the area of the underlying conductive part 22b would provide the most effective arrangement for discharging trapped carriers at the second semiconductor layer interface thereby eliminating current collapse in the region, achieving the goal of suppressing on-resistance of the device.
Regarding claim 14, Kajiwara discloses:
wherein forming the conductive part includes:
forming a conductive film (22b/22F) on the second semiconductor layer; and
removing a protion of the conductive film (para 0083; portion 22F removed).
Although Kajiwara does not specifically disclose “wet etching” as the removal process. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that wet and dry etching processes are well known applications for film removal of various types within the semiconductor industry.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERROL V FERNANDES/Primary Examiner, AU 2893