DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR DEVICE WITH A FIELD PLATE LOCATED IN An INTER-LAYER INSULATING FILM
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 8,9 and 13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Fukui (US 20170301788), hereinafter Fukui.
Regarding claim 1, Fukui (US 20170301788) (see markup of Figure 2 below; also see Figures 1-4; also applies to embodiment of Figure 14, which has similar labels for equivalent parts) teaches a semiconductor device (described as “silicon carbide MOSFET” in para 31), comprising:
a silicon carbide layer (“substrate” of the device is described as being “silicon carbide” – see para 36, and 3,4, 5 are formed in this substrate) including
a first surface (labelled S1 in markup of Figure 2 below),
a second surface (labelled S2 in markup of Figure 2 below),
a third surface (labelled S3 in markup of Figure 2 below) positioned at a side opposite to the first and second surfaces in a first direction (i.e. vertical direction in orientation of Figure 2, i.e. S1, S2 and S3 are horizontal surfaces in orientation of Figure 2 and spaced apart in vertical direction of Figure 2), and
a side surface (labelled SS in markup of Figure 2 below), the second surface being positioned between the first surface and the side surface in a direction orthogonal to (i.e. SS is a vertical surface in orientation of Figure 2) the first direction, the second surface (S2) being at a position recessed further toward (best seen in markup of Figure 2) the third surface (S3) side than the first surface (S1);
a first electrode (10, described as “source electrode 10” in para 35) located at the first surface (S1);
a second electrode (11, described as “drain electrode 11” in para 35) located at the third surface (S3);
a gate electrode (8, described as “gate electrode 8” in para 34) located in the silicon carbide layer between the first surface (S1) and the third surface (S3);
a gate insulating film (7, described as “gate insulating film 7” in para 37) located between the gate electrode (8) and the silicon carbide layer (i.e. substrate);
an inter-layer insulating film (9, described as “interlayer-insulation film 9” in para 35; also additionally labelled ILD > 9 on markup of Figure 2) located on the second surface (S2),
a thickness of the inter-layer insulating film (see thickness of 9 in region of 40) being greater than a difference in heights in the first direction (i.e. vertical direction in orientation of in Figure 2) between the first surface (S1) and the second surface (S2); and
a field plate (20, described as “gate line 20” in para 34, which is made from “polysilicon 25” – see Figure 9 and para 60 and 66) located in the inter-layer insulating film (9), the field plate having a lower resistivity than the inter-layer insulating film (inherent as gate line is made of polysilicon so that it can transmit electrical signals while inter-layer insulating film does not as it is an insulator having very high electrical resistivity).
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Regarding claim 2, Fukui teaches the device according to claim 1, wherein the field plate (20) is positioned within a range from the second surface (S2) to a height in the first direction (i.e. vertical direction in Figure 2) of the first surface (S1); also see 35 USC 112, 2nd paragraph rejection above.
Regarding claim 3, Fukui teaches the device according to claim 1, wherein the silicon carbide layer includes:
a first layer (3, described as “n-type drift layer 3” in para 36) provided continuously between the first surface (S1) and the third surface (S3) and between the second surface (S2) and the third surface (S3), the first layer being of a first conductivity type (i.e. n-type, as explained above);
a second layer (4, described as “p-type well region 4” in para 36) located on the first layer, the second layer facing a side surface of the gate electrode via the gate insulating film, the second layer being of a second conductivity type (i.e. p-type, as explained above);
a third layer (5, described as “n-type source region 5” in para 36) located on the second layer, the third layer (5) being of the first conductivity type (i.e. n-type, as explained above) and having a higher (see para 120, which describes “impurity concentration of the drift layer 3 lower than that of the source regions 5”) first-conductivity-type impurity concentration than the first layer (3), the third layer (5; i.e. the “n-type source region 5”, as explained above) being electrically connected with the first electrode (10, described as “source electrode 10” in para 35);
a fourth layer (1) located between the first layer (3) and the second electrode (11; i.e. drain electrode), the fourth layer being electrically connected with the second electrode (i.e. to drain electrode – see Figure 2); and
a fifth layer (13, described as “field grading regions 13” in para 35, which are p-type – see para 38, especially 1st sentence) positioned under the gate electrode (8) in the first layer (3), the fifth layer contacting (best seen in Figure 2 or it’s markup) the gate insulating film (7) located at a bottom surface of the gate electrode, the fifth layer (13) being of the second conductivity type (i.e. p-type, as explained above).
Regarding claim 4, Fukui teaches the device according to claim 3, wherein the silicon carbide layer further includes a sixth layer (12, described as “p-type termination electric field grating region 12” in para 42) positioned under (see markup of Figure 2) the second surface (S2) in the first layer (3), the sixth layer (12) is positioned at a same height (as 12 and 13 are made from the same layer – see Figure 9 and para 57, especially 1st sentence) as the fifth layer (13) in the first direction, and the sixth layer is of the second conductivity type (i.e. p-type, as explained above).
Regarding claim 6, Fukui teaches the device according to claim 4, wherein the sixth layer (12) has a second-conductivity-type impurity (i.e. p-type, as explained in para 42) concentration gradient in which a second-conductivity-type impurity concentration of the sixth layer proximate to the side surface is less than the second-conductivity-type impurity concentration of the sixth layer proximate to the gate electrode (see para 57, especially last sentence).
Regarding claim 8, Fukui teaches the device according to claim 1, wherein a thickness of the inter-layer insulating film (9) on the second surface (S2) is greater (best seen in markup of Figure 2) than a thickness of the inter-layer insulating film on the first surface (S1, especially see first surface S1 where gate electrode 8 region is located).
Regarding claim 9, Fukui teaches the device according to claim 1, wherein the inter-layer insulating film (9) covers an interface between (best seen in markup of Figure 2) the first surface (S1) and the second surface (S2).
Regarding claim 13, Fukui teaches the device according to claim 3, wherein the fifth layer (13) is electrically connected with the first electrode (10, described as “source electrode 10” in para 35) – see para 38 which describes “3 may be in contact with or spaced apart from the well region 4” and well region 4 is connected to 10 by ”contact regions 16” – see Figure 2; , also see para 43 that describes "the source electrode 10 is formed in contact with the source regions 5 and the well contact regions 16 ")
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Fukui.
Regarding claim 5, Fukui teaches the device according to claim 4, but does not clearly teach that the sixth layer (12) includes “a plurality of guard ring layers”. However, Fukui teaches that the sixth layer (12) is "known as a region having p-type impurities having an electric field grading effect", such as "a field limiting ring (FLR) region" as a region formed around cell region 30 in which “MOSFET cells are arranged to prevent a semiconductor device from breaking due to the concentration of an electric field at the outermost circumference of the cell region 30” (para 80). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Fukui so that the sixth layer (12) includes “a plurality of guard ring layers”. The ordinary artisan would have been motivated to modify Fukui for at least the purpose of prevent a semiconductor device from breaking due to the concentration of an electric field at the outermost circumference of the cell region (para 80 of Fukui).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fukui in view of Kim (US 20220190105), hereinafter Kim.
Regarding claim 10, Fukui teaches the device according to claim 1, but does not teach wherein the field plate (20) is formed “in a plurality of ring shapes”. Kim (US 20220190105) teaches a similar semiconductor device (described as “silicon carbide (SiC) MOSFET” in para 58), comprising a field plate (36a or 36b or 36c – see para 40 and 50), wherein the field plate may be formed in a plurality of ring shapes (see “ring shape of a closed loop” as one of the options in para 41). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Fukui so that the field plate (20) is formed “in a plurality of ring shapes”. The ordinary artisan would have been motivated to modify Fukui for at least the purpose of distributing the voltage more uniformly (also see para 41 and 69 of Kim).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Fukui in view of Matsudai (US 20160035840), hereinafter Matsudai .
Regarding claim 11, Fukui teaches the device according to claim 1, but does not teach wherein the field plate is “electrically floating”. Matsudai teaches a similar device wherein field plates may be set to be in the floating state (para 65). It would have been obvious to one of ordinary skills in the art at the time of the effective filing of the claimed invention to modify Fukui so that t the field plate is “electrically floating”. The ordinary artisan would have been motivated to modify Fukui for at least the purpose of setting the potential gradient more gradual, which can assist in a design that suppresses the element breakdown of specific regions (para 65 of Matsudai).
Allowable Subject Matter
Claims 7, 12 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 is allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations that require “he second surface continuously surrounds the first surface”.
Claim 12 is allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations that require “the field plate is electrically connected with the first electrode”.
Claim 14 is allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations that require “the field plate is electrically connected with the first electrode”.
Claim 15 is allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations that require “a second-conductivity-type impurity concentration of the fifth layer is greater than a second-conductivity-type impurity concentration of the second layer”.
Claim 16 is allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations that require “wherein the sixth layer is electrically connected with the first electrode”.
Claim 17 is allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations that require “a first-conductivity-type impurity concentration of the field stop layer is greater than the first-conductivity-type impurity concentration of the first layer”.
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892