DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 02/09/2026 Amendment.
Claims 6-22, 24-25 are pending and examined. Claims 1-5, 23 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-22, 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over US 9,472,261 to Chun et al. (hereafter Chun) in view of US 7,929,368 to Jeddeloh (hereafter Jeddeloh).
Regarding independent claim 6, Chun teaches a non-transitory computer readable apparatus comprising a storage medium having a plurality of computer-readable instructions (instructions to perform steps in FIGS. 2-3), the plurality of computer- readable instructions being configured to, when executed by a processing apparatus:
receive first data identifying a prescribed minimum level of performance for use during operation of a volatile memory device (FIG. 1: e.g. receiving calibration data according to LUT table 167, which comprises minimum level of performance for use at temperature T1 or T2, see 3:42-45 and 5:13-6:46);
access a data structure (LUT 167 of FIG. 1 is seen as statistically-based information when it is applied to the DRAM) comprising:
second data identifying a plurality of performance values or ranges (e.g. identifying performance values of error rate of 0, error rate of 1, and error rate of 2 corresponding to the temperature, see 3:42-45 and 5:13-6:46); and
third data associated with a refresh rate for the respective ones of the plurality of performance values or ranges (FIG. 1: e.g. refresh rates R1-R3 according to error rates in LUT 167);
based at least on the received first data, select one of the third data (FIG. 1: based on the temperature, selecting one of the refresh rates R1-R3 corresponding to selected error rate, also see 5:13-6:46); and
cause operation of the volatile memory device with a refresh rate associated with the selected one of the third data (FIG. 5: refresh the DRAM in step 520 with selected refresh rate),
Jeddeloh teaches error rates are tracked for different regions within a memory device for refresh rates, wherein the refresh rates comprises a probabilistic refresh scheme (FIG. 3: e.g. comprising memory map 315 and MVEL 324, see 4:43-51) that causes different memory cells or regions of the volatile memory device to be refreshed at different rates based on the probabilistic refresh scheme (see FIG. 4 and 6:31-47).
Since Chun and Jeddeloh are both from the same field of endeavor, the purpose disclosed by Jeddeloh would have been recognized in the pertinent art of Chun.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to refresh different regions of memory device at different refresh rate as needed in order to maximize the performance of the memory device (see 5:53-63).
Regarding dependent claim 7, Chun teaches wherein the second data and third data of the data structure are based at least in part on a probabilistic characterization of the memory device (error rate and refresh rate are considered probabilistic considerations).
Regarding dependent claim 8, Jeddeloh teaches wherein the plurality of computer-readable instructions are further configured to, when executed by a processing apparatus: receive fourth data indicative of a parameter associated with the volatile memory device (FIG. 1: data from MVEL 324 for tracking different error rates); evaluate the received fourth data indicative of the parameter; and cause, based at least on evaluation of the received fourth data: selection of a different one of the third data from the data structure; and operation of the volatile memory device with a refresh rate associated with the selected different one of the third data (determining a refresh rate corresponding to the new error rate).
Regarding dependent claim 9, Chun teaches wherein the first data identifying the prescribed minimum level of performance is based on at least one of a type of application using the volatile memory device, a user of the application, or a predetermined level of granularity for control of the volatile memory device (i.e. error rate is considered granularity for control of the DRAM).
Regarding dependent claim 10, Chun teaches wherein the plurality of performance values or ranges comprises information on how the volatile memory device functions based on a given temperature of operation of the volatile memory device (FIG. 1: see T1 and T2 of LUT 167).
Regarding dependent claim 11, Jeddeloh teaches wherein the plurality of performance values or ranges comprises a map of performance of the volatile memory device as a function of one or more parameters (FIG. 3: memory map 315 and MVEL 324).
Regarding dependent claim 12, Chun teaches wherein the one or more parameters comprises at least a voltage of operation of the volatile memory device (because the refresh rate depends on whether the DRAM/SOC device is operated in power saving mode or in active mode, see 5:35-10:24).
Regarding independent claim 13, Chun teaches a computing device (see FIG. 1) comprising:
a volatile memory device (FIG. 1: DRAM 120); and
a processing apparatus (FIG. 1: SOC 110) configured to:
receive first data indicative of a prescribed minimum level of performance of operation of the volatile memory device (FIG. 1: e.g. receiving calibration data according to LUT table 167, which comprises minimum level of performance for use at temperature T1 or T2, see 3:42-45 and 5:13-6:46);
access a data structure (LUT 167 of FIG. 1 is seen as statistically-based information when it is applied to the DRAM) comprising:
second data identifying a plurality of performance values or ranges (e.g. identifying performance values of error rate of 0, error rate of 1, and error rate of 2 corresponding to the temperature, see 3:42-45 and 5:13-6:46); and
third data associated with a refresh rate of the respective ones of the plurality of performance values or ranges (FIG. 1: e.g. refresh rates R1-R3 according to error rates in LUT 167);
based at least on the received first data, select one of the third data (FIG. 1: based on the temperature, selecting one of the refresh rates R1-R3 corresponding to selected error rate, also see 5:13-6:46); and
cause operation of the volatile memory device with a refresh rate associated with the selected one of the third data (FIG. 5: refresh the DRAM in step 520 with selected refresh rate),
Jeddeloh teaches error rates are tracked for different regions within a memory device for refresh rates, wherein the refresh rates comprises a probabilistic refresh scheme (FIG. 3: e.g. comprising memory map 315 and MVEL 324, see 4:43-51) that causes different memory cells or regions of the volatile memory device to be refreshed at different rates based on the probabilistic refresh scheme (see FIG. 4 and 6:31-47).
Since Chun and Jeddeloh are both from the same field of endeavor, the purpose disclosed by Jeddeloh would have been recognized in the pertinent art of Chun.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to refresh different regions of memory device at different refresh rate as needed in order to maximize the performance of the memory device (see 5:53-63).
Regarding dependent claims 14-17, 19, see rejections applied to claims 7-11 above.
Regarding dependent claim 18, Chun teaches wherein the given temperature comprises an on-die measurement of the volatile memory device (FIG. 1: temperature sensor 122 is in DRAM 120).
Regarding dependent claim 20, Chun teaches wherein the one or more parameters comprises at least one of temperature, voltage, load, or user activity (because the refresh rate depends on whether the DRAM/SOC device is operated in power saving mode or in active mode, see 5:35-10:24. The power saving mode or active mode are related to user activity).
Regarding dependent claim 21, Chun teaches wherein the one or more parameters comprises at least one of an on-die temperature or an ambient temperature (FIG. 1: temperature obtained from temperature sensor 122 is in DRAM 120 is on-die temperature).
Regarding independent claim 22, Chun teaches a method comprising:
receiving first data indicative of a prescribed minimum level of performance of operation of a volatile memory device (FIG. 1: e.g. receiving calibration data according to LUT table 167, which comprises minimum level of performance for use at temperature T1 or T2, see 3:42-45 and 5:13-6:46);
accessing a data structure comprising:
second data identifying a plurality of performance values or ranges (e.g. identifying performance values of error rate of 0, error rate of 1, and error rate of 2 corresponding to the temperature, see 3:42-45 and 5:13-6:46); and
third data associated with a refresh rate of the respective ones of the plurality of performance values or ranges (FIG. 1: e.g. refresh rates R1-R3 according to error rates in LUT 167),
wherein the second data and third data of the data structure are based on least in part on probabilistic characterization of the memory device (LUT 167 of FIG. 1 is seen as statistically-based information when it is applied to the DRAM);
based at least on the received first data, selecting one of the third data (FIG. 1: based on the temperature, selecting one of the refresh rates R1-R3 corresponding to selected error rate, also see 5:13-6:46); and
causing operation of the volatile memory device with a refresh rate associated with the selected one of the third data (FIG. 5: refresh the DRAM in step 520 with selected refresh rate),
Jeddeloh teaches error rates are tracked for different regions within a memory device for refresh rates, wherein the refresh rates comprises a probabilistic refresh scheme (FIG. 3: e.g. comprising memory map 315 and MVEL 324, see 4:43-51) that causes different memory cells or regions of the volatile memory device to be refreshed at different rates based on the probabilistic refresh scheme (see FIG. 4 and 6:31-47).
Since Chun and Jeddeloh are both from the same field of endeavor, the purpose disclosed by Jeddeloh would have been recognized in the pertinent art of Chun.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to refresh different regions of memory device at different refresh rate as needed in order to maximize the performance of the memory device (see 5:53-63).
Regarding dependent claims 24-25, see rejection applied to claims 7-9.
Response to Arguments
Applicant’s arguments, filed on 02/09/2026, with respect to the rejection of claims 6, 13 and 22 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of additional reference to Jeddeloh as stated above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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February 19, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824