DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moll et al. (US 20080128773 A1, hereinafter Moll)
With regards to claim 1, Moll discloses a semiconductor structure, (FIGS. 1-2A) comprising:
a transistor; (transistor 5)
a contact (contact 24, 58) located on the transistor and coupled with a first active area (source/drain 51) of the transistor; and
a capacitive structure (capacitor 2, see FIGS. 1-2A) located over the contact, wherein an extending direction of a sidewall of the capacitive structure at an end adjacent to the contact overlaps an extending direction of a sidewall of the contact, (see FIG. 1, showing the overlap between the horizontal sidewall of the contact and the horizontal sidewall of the capacitor in a direction away from the substrate) and one electrode of the capacitive structure is coupled with the contact, (See FIG. 1)
wherein at least a part of the capacitive structure and the contact are confined within one and the same opening. (See FIG. 1, showing opening defined by portions of 54, 38, 71, and 76 containing layers 58, 24, and 2. See also response to Arguments)
With regards to claim 2, Moll discloses the semiconductor structure of claim 1, wherein the opening includes an opening sidewall comprising the sidewall of the capacitive structure and sidewall of the contact. (see FIGS. 1-2B, showing the opening defined by portions of 54, 38, 71, and 76 containing sidewalls of layers 58, 24, and 2. See also response to Arguments)
With regards to claim 3, Moll discloses the semiconductor structure of claim 1, wherein the contact comprises a connecting layer (contact 58) and a conductive part, (contact 24) and the connecting layer is located between the first active area and the conductive part. (See FIG. 1)
With regards to claim 4, Moll discloses the semiconductor structure of claim 1, wherein the capacitive structure comprises:
a first sub capacitor (capacitor portion 211) and a second sub capacitor; (capacitor portion 212) and
a first sidewall (sidewall of portion 211) extending in a first direction and a second sidewall (horizontal sidewall between 211 and 212) extending in a second direction crossing the first direction, wherein the second sidewall extends along an interface between the first sub capacitor and the second sub capacitor. (See FIG. 2A, showing the extension)
With regards to claim 5, Moll discloses the semiconductor structure of claim 4, further comprising an insulating layer (insulation layer 71) located over the first active area, wherein the capacitive structure penetrates through the insulating layer. (see FIG. 1)
With regards to claim 6, Moll discloses the semiconductor structure of claim 5, wherein the insulating layer comprises a first sub insulating layer (insulation layer 71) and a second sub insulating layer, (insulation layer 76)
the first sub insulating layer is located between the second sub insulating layer and the contact, (see FIG. 1, showing the positioning)
the first sub capacitor penetrates through the first sub insulating layer in a third direction perpendicular to the second direction and is coupled with the contact, (see FIGS. 1 and 2A, where the capacitor 211 of FIG. 2 penetrates through insulation layer 71)
the second sub capacitor penetrates through the second sub insulating layer in the third direction, and (see FIGS. 1 and 2A, where the capacitor 212 of FIG. 2 penetrates through insulation layer 76)
the second sidewall extends along an interface between the first sub insulating layer and the second sub insulating layer. (see FIGS. 1 and 2A, where the horizontal portion of capacitor 2 of FIG. 2 extends along the interface between insulation layers 71 and 76)
With regards to claim 7, Moll discloses the semiconductor structure of claim 6, wherein a size of the second sub capacitor at an end adjacent to the transistor in the second direction is smaller than a size of the first sub capacitor at an end away from the transistor in the second direction. (see FIG. 2A, showing the second sub capacitor having a smaller end than the first sub capacitor)
With regards to claim 8, Moll discloses the semiconductor structure of claim 3, wherein a thickness of the conductive part is larger than a thickness of the connecting layer in a third direction. (see FIG. 1, showing the thickness of contact 24 is larger than the thickness of contact 58 from left to right)
With regards to claim 9, Moll discloses the semiconductor structure of claim 8, wherein the thickness of the conductive part is larger than or equal to twice of the thickness of the connecting layer in the third direction. (see FIG. 1, showing the thickness of contact 24 is at least twice as large the thickness of contact 58 from left to right)
With regards to claim 10, Moll discloses the semiconductor structure of claim 3, wherein the contact further comprises a buffering layer, and the connecting layer is located between the buffering layer and the conductive part.
With regards to claim 12, Moll discloses the semiconductor structure of claim 1, wherein the capacitive structure comprises:
a first electrode, (electrode 21) a dielectric layer (dielectric 22) and a second electrode (electrode 23) disposed sequentially, wherein the first electrode is coupled with the contact, and a plurality of the capacitive structures are coupled by the second electrode. (See FIGS. 1 and 2A, where the second electrode 23 couples multiple capacitors 2)
With regards to claim 13, Moll discloses a memory system, (FIGS. 1-2A) comprising:
a memory device comprising:
a transistor; (transistor 5)
a contact (contact 24,58) located on the transistor and coupled with a first active area (source/drain 51) of the transistor; (See FIG. 1) and
a capacitive structure (capacitor 2, see FIGS. 1-2A) located over the contact, wherein an extending direction of a sidewall of the capacitive structure at an end adjacent to the contact overlaps an extending direction of a sidewall of the contact, (see FIG. 1, showing the overlap between the horizontal sidewall of the contact and the horizontal sidewall of the capacitor in a direction away from the substrate) and one electrode of the capacitive structure is coupled with the contact; and
a memory controller (peripheral circuitry connected to access transistor 5) coupled with the memory device and controlling the memory device. (See at least Paragraphs [0039] and [0073])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moll et al. (US 20080128773 A1, hereinafter Moll)
With regards to claim 11, Moll discloses the semiconductor structure of claim 10, wherein the first active area comprises single crystal silicon or polysilicon, (silicon substrate, see Paragraph [0042]).
However, Moll does not explicitly teach the connecting layer comprises metal silicide, and the buffering layer comprises single crystal silicon or polysilicon.
It should be noted that metal silicides and single crystal silicon/polysilicon are well-known conductive materials that can be substituted to obtain predictable results.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Moll to have the specific conductive materials as recited above.
Response to Arguments
Applicant's arguments filed 04/23/2026 have been fully considered but they are not persuasive.
Examiner notes that, based on the amendments to the claims, the rejection under 35 USC 112b is hereby rescinded.
However, Examiner notes that the amendments to the claims do not overcome the current rejection over 35 USC 102.
Examiner notes that the opening which contains the contact 24/58 is in direct contact and direct communication with the opening which contains the capacitor 2. Based on broadest reasonable interpretation, the opening which contains the contact 24/58 and the capacitor can be considered one opening. This is consistent with the Specification, as FIG. 1d shows multiple dielectric layers which contain the opening for layers 120 and 140.
Therefore, at least claims 1 and 13 are properly rejected, and claims 2-12 are rejected for at least their dependencies.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cho et al. (US 20210202490 A1) – multi-layered structure with aligned sidewalls.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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