DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 12/01/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 7, and 13 recite “…at an end proximate to the [contact]…” Merriam Webster defines ‘proximate” as “very close, near.” However, Applicant has not defined how close or near something must be to be “proximate” to the contact. Thus, there is ambiguity as to where the layers must be to meet the limitations of “proximate.”
Therefore, claims 1, 7, and 13 are rejected under 35 USC 112b for being indefinite, and claims 2-12 are rejected for at least their dependencies.
For the purposes of Examination, any distance will be considered to meet the limitations of “proximate.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moll et al. (US 20080128773 A1, hereinafter Moll)
With regards to claim 1, Moll discloses a semiconductor structure, (FIGS. 1-2A) comprising:
a transistor; (transistor 5)
a contact (contact 31,35) located on the transistor and coupled with a first active area (source/drain 51) of the transistor; and
a capacitive structure (capacitor 2, see FIGS. 1-2A) located over the contact, wherein an extending direction of a sidewall of the capacitive structure at an end proximate to the contact overlaps an extending direction of a sidewall of the contact, (see FIG. 1m, showing the overlap between the horizontal sidewall of the contact and the vertical sidewall of the capacitor) and one electrode of the capacitive structure is coupled with the contact. (See FIG. 1)
With regards to claim 2, Moll discloses the semiconductor structure of claim 1, wherein at least a part of the capacitive structure and the contact are confined within one and the same opening. (see FIGS. 1-2B, showing the layers in the same opening)
With regards to claim 3, Moll discloses the semiconductor structure of claim 1, wherein the contact comprises a connecting layer (contact 58) and a conductive part, (contact 24) and the connecting layer is located between the first active area and the conductive part.
With regards to claim 4, Moll discloses the semiconductor structure of claim 1, wherein the capacitive structure comprises:
a first sub capacitor (capacitor portion 211) and a second sub capacitor; (capacitor portion 212) and
a first sidewall (sidewall of portion 211) extending in a first direction and a second sidewall (horizontal sidewall between 211 and 212) extending in a second direction crossing the first direction, wherein the second sidewall extends along an interface between the first sub capacitor and the second sub capacitor. (See FIG. 2A, showing the extension)
With regards to claim 5, Moll discloses the semiconductor structure of claim 4, further comprising an insulating layer (insulation layer 71) located over the first active area, wherein the capacitive structure penetrates through the insulating layer. (see FIG. 1)
With regards to claim 6, Moll discloses the semiconductor structure of claim 5, wherein the insulating layer comprises a first sub insulating layer (insulation layer 71) and a second sub insulating layer, (insulation layer 76)
the first sub insulating layer is located between the second sub insulating layer and the contact, (see FIG. 1, showing the positioning)
the first sub capacitor penetrates through the first sub insulating layer in a third direction perpendicular to the second direction and is coupled with the contact, (see FIGS. 1 and 2A, where the capacitor 211 of FIG. 2 penetrates through insulation layer 71)
the second sub capacitor penetrates through the second sub insulating layer in the third direction, and (see FIGS. 1 and 2A, where the capacitor 212 of FIG. 2 penetrates through insulation layer 76)
the second sidewall extends along an interface between the first sub insulating layer and the second sub insulating layer. (see FIGS. 1 and 2A, where the horizontal portion of capacitor 2 of FIG. 2 extends along the interface between insulation layers 71 and 76)
With regards to claim 7, Moll discloses the semiconductor structure of claim 6, wherein a size of the second sub capacitor at an end proximate to the transistor in the second direction is smaller than a size of the first sub capacitor at an end away from the transistor in the second direction. (see FIG. 2A, showing the second sub capacitor having a smaller end than the first sub capacitor)
With regards to claim 8, Moll discloses the semiconductor structure of claim 3, wherein a thickness of the conductive part is larger than a thickness of the connecting layer in a third direction. (see FIG. 1, showing the thickness of contact 24 is larger than the thickness of contact 58 from left to right)
With regards to claim 9, Moll discloses the semiconductor structure of claim 8, wherein the thickness of the conductive part is larger than or equal to twice of the thickness of the connecting layer in the third direction. (see FIG. 1, showing the thickness of contact 24 is at least twice as large the thickness of contact 58 from left to right)
With regards to claim 10, Moll discloses the semiconductor structure of claim 3, wherein the contact further comprises a buffering layer, and the connecting layer is located between the buffering layer and the conductive part.
With regards to claim 12, Moll discloses the semiconductor structure of claim 1, wherein the capacitive structure comprises:
a first electrode, (electrode 21) a dielectric layer (dielectric 22) and a second electrode (electrode 23) disposed sequentially, wherein the first electrode is coupled with the contact, and a plurality of the capacitive structures are coupled by the second electrode. (See FIGS. 1 and 2A, where the second electrode 23 couples multiple capacitors 2)
With regards to claim 13, Moll discloses a memory system, (FIGS. 1-2A) comprising:
a memory device comprising:
a transistor; (transistor 5)
a contact (contact 31,35) located on the transistor and coupled with a first active area (source/drain 51) of the transistor; and
a capacitive structure (capacitor 2, see FIGS. 1-2A) located over the contact, wherein an extending direction of a sidewall of the capacitive structure at an end proximate to the contact overlaps an extending direction of a sidewall of the contact, (see FIG. 1, showing the overlap between the horizontal sidewall of the contact and the vertical sidewall of the capacitor) and one electrode of the capacitive structure is coupled with the contact; and
a memory controller (peripheral circuitry connected to access transistor 5) coupled with the memory device and controlling the memory device. (See at least Paragraphs [0039] and [0073])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moll et al. (US 20080128773 A1, hereinafter Moll)
With regards to claim 11, Moll discloses the semiconductor structure of claim 10, wherein the first active area comprises single crystal silicon or polysilicon, (silicon substrate, see Paragraph [0042]).
However, Moll does not explicitly teach the connecting layer comprises metal silicide, and the buffering layer comprises single crystal silicon or polysilicon.
It should be noted that metal silicides and single crystal silicon/polysilicon are well-known conductive materials that can be substituted to obtain predictable results.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Moll to have the specific conductive materials as recited above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cho et al. (US 20210202490 A1) – multi-layered structure with aligned sidewalls.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812