DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 05/22/2026 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Response to Arguments
Applicant's arguments filed 07/01/2026 have been fully considered but they are not persuasive.
As to claims 1 and 11, Applicant argues that Oh fails to teach the flow prevention structures contacting the test pad. Examiner disagrees, and notes that the amended claim language does not state that they must directly contact one another. While the flow prevention structures do not directly contact the test pad, they do contact one another via the wiring layer 135. As to the argument of the flow prevention structures not being disposed between adjacent ones of the conductive bumps, upon further consideration, Examiner has identified the flow prevention structures and test pad region within the recited limitations in a new way as set forth below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al. (US 2021/0134761 A1), hereafter “Oh”.
As to claim 1, Oh teaches a semiconductor package (1000, Fig. 1B, ⁋ [0025]), comprising:
a first semiconductor chip (200) including:
a first substrate (201, ⁋ [0026]) comprising a second surface (top surface);
a plurality of through electrodes (210) extending in the first substrate; and
first bonding pads (212, ⁋ [0029]) on the second surface of the first substrate,
wherein the first bonding pads are electrically connected to the plurality of through electrodes (⁋ [0029]);
a second semiconductor chip (100) including:
a second substrate (101, ⁋ [0039]) comprising a first surface (bottom surface);
a second wiring layer (135, ⁋ [0041]) on the first surface of the second substrate;
redistribution pads (130Pd, ⁋⁋ [0039]-[0042]) in the second wiring layer;
second bonding pads (141, ⁋⁋ [0047]-[0048]) on the redistribution pads;
first conductive bumps (143, Fig. 1B, ⁋⁋ [0047]-[0048]) between the first bonding pads and the second bonding pads; and
a test pad region (see annotated Fig. 1B below), between the first conductive bumps, wherein the test pad region comprises a test pad (130Pt, ⁋ [0042]) in the second wiring layer,
wherein the second semiconductor chip (100) is stacked on the first semiconductor chip (200) via the first conductive bumps (143 of 140);
an adhesive layer (150, ⁋ [0025]) between the first semiconductor chip (200) and the second semiconductor chip (100), wherein the adhesive layer is disposed between the first conductive bumps (143 of 140); and
flow prevention structures (140D1+140D2, ⁋⁋ [0045], [0063]) in the adhesive layer and contacting the test pad, wherein the flow prevention structures are disposed in the test pad region (see annotated Fig. 1B) between adjacent ones of the first conductive bumps (140D1 of Fig. 1B is located between both 143 of 140).
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As to claim 2, Oh teaches the semiconductor package of claim 1, wherein the adhesive layer (150) includes a non-conductive film (NCF) (⁋ [0051]).
As to claim 10, Oh teaches the semiconductor package of claim 1, further comprising:
a package substrate (300, Fig. 7, ⁋ [0055]), and
wherein the first semiconductor chip (200) is mounted on the package substrate via second conductive bumps (240, ⁋ [0026]) (⁋ [0093]).
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-5, and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Oh, and further in view of Lee et al. (US 2020/0135594 A1), hereafter “Lee”.
As to claim 3, Oh teaches the semiconductor package of claim 1, wherein the flow prevention structures (140D2) include a dummy pad (141 of 140D2, Fig. 1B, ⁋⁋ [0047]-[0048]) and a dummy bump (143 of 140D2, Fig. 1B, ⁋⁋ [0047]-[0048]) on the dummy pad.
Oh fails to teach wherein the dummy pad, of the flow prevention structure, is on a test pad.
Lee teaches a similar semiconductor package (1a, Fig. 8, ⁋ [0059]) wherein a test pad (TP, ⁋ [0065]) overlaps a dummy pad (DP) (Fig. 8+Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the test pad overlapping a dummy pad as taught by Lee into the device of Oh for the purpose of reducing the thickness of the semiconductor package and efficiently discharge heat in the chips externally through pads coupled to each other while being in contact with each other (⁋ [0103]).
As to claim 4, Oh in view of Lee teach the semiconductor package of claim 3, Oh further teaches wherein the dummy bump (143 of 140D2) includes a same material as the first conductive bumps (143 of 140D1) (⁋ [0048], “dummy bump 140D may include a first dummy bump 140D1 and a second dummy bump 140D2”).
As to claim 5, Oh in view of Lee teach the semiconductor package of claim 3, Oh further teaches wherein the dummy pad (141 of 140D2) includes a same material as the second bonding pads (141 of 140D1) (⁋ [0048], “dummy bump 140D may include a first dummy bump 140D1 and a second dummy bump 140D2”).
As to claim 11, Oh teaches a semiconductor package (1000, Fig. 1B, ⁋ [0025]), comprising:
a first semiconductor chip (200) including:
a first substrate (201, ⁋ [0026]) having a first surface (bottom surface) and a second surface (top surface) opposite to the first surface;
a plurality of through electrodes (210) penetrating the first substrate;
first bonding pads (230, ⁋ [0026]) on the first surface, wherein the first bonding pads are electrically connected to the plurality of through electrodes (⁋ [0032]); and
second bonding pads (212, ⁋ [0029]) on the second surface, wherein the second bonding pads are electrically connected to the plurality of through electrodes (⁋ [0029]);
a second semiconductor chip (100) including:
a second substrate (101, ⁋ [0039]) having a third surface (bottom surface) and a fourth surface (top surface) opposite to the third surface;
a second wiring layer (135, ⁋ [0041]) on the third surface of the second substrate; and
third bonding pads (141 of 140D1, ⁋⁋ [0047]-[0048]) on the second wiring layer,
wherein the second semiconductor chip (100) is on the second surface of the first substrate (Fig. 1B),
wherein the second wiring layer includes redistribution pads (130Pd, ⁋⁋ [0039]-[0042]) and test pads (130Pt, ⁋ [0042]), and
wherein the third bonding pads (141 of 140D1) are on the redistribution pads (130Pd) (⁋ [0042], “the dummy pad 130Pd may be a pad on which the first dummy bump 140D1 is provided”);
conductive bumps (143, Fig. 1B, ⁋⁋ [0047]-[0048]) between the first semiconductor chip and the second semiconductor chip and electrically connecting the second bonding pads (212) and the third bonding pads (141 of 140D1) (⁋ [0047]);
an adhesive layer (150, ⁋ [0025]) between the first semiconductor chip (100) and the second semiconductor chip, wherein the adhesive layer is in a space between the conductive bumps (143 of 140) (Fig. 1B); and
flow prevention structures (140D1+140D2, ⁋⁋ [0045], [0063]) in the adhesive layer and contacting the test pad (140D2 contacts 130Pt via 135),
wherein the flow prevention structures are disposed between adjacent ones of the conductive bumps (140D1 of Fig. 1B is located between both 143 of 140).
Oh fails to teach wherein the flow prevention structures overlap the test pads viewed from a plan view, however, Examiner notes that Oh does teach the flow prevention structure comprising of a dummy pad and a dummy bump connected thereto.
Lee teaches a similar semiconductor package (1a, Fig. 8, ⁋ [0059]) wherein a test pad (TP, ⁋ [0065]) overlaps a dummy pad (DP) (Fig. 8+Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the test pad overlapping a dummy pad as taught by Lee into the device of Oh for the purpose of reducing the thickness of the semiconductor package and efficiently discharge heat in the chips externally through pads coupled to each other while being in contact with each other (⁋ [0103]).
As to claim 12, Oh in view of Lee teach the semiconductor package of claim 11, Oh further teaches wherein the adhesive layer (150) includes a non-conductive film (NCF) (⁋ [0051]).
As to claim 13, Oh in view of Lee teach the semiconductor package of claim 11, and further teaches wherein the flow prevention structures of Oh (140D2) include a dummy pad (141 of 140D2) on the modified test pads of Lee (TP, Fig. 9, see claim 11) and Oh’s dummy bump (143 of 140D2) on the dummy pad (Fig. 1B of Oh).
As to claim 14, Oh in view of Lee teach the semiconductor package of claim 13, Oh further teaches wherein the dummy bump (143 of 140D2) includes a same material as the conductive bumps (143 of 140D1) (⁋ [0048], “dummy bump 140D may include a first dummy bump 140D1 and a second dummy bump 140D2”).
As to claim 15, Oh in view of Lee teach the semiconductor package of claim 14, Oh further teaches wherein the dummy bump (143 of 140D2) has a diameter same as a diameter of the conductive bumps (143 of 140D1) (⁋ [0079], “the sizes of the second bump 140 and the dummy bump 140D”).
As to claim 16, Oh in view of Lee teach the semiconductor package of claim 13, Oh further teaches wherein the dummy pad (141 of 140D2) includes a same material as the third bonding pads (141 of 140D1) (⁋ [0048], “dummy bump 140D may include a first dummy bump 140D1 and a second dummy bump 140D2”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CARNELL HUNTER III/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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