Prosecution Insights
Last updated: April 19, 2026
Application No. 18/456,295

PACKAGE COMPRISING A SUBSTRATE WITH AN EMBEDDED FRAME

Non-Final OA §102§112
Filed
Aug 25, 2023
Examiner
CHOWDHARY, NIMARTA KAUR
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant

Examiner Intelligence

Grants only 0% of cases
0%
Career Allow Rate
0 granted / 0 resolved
-68.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
10 currently pending
Career history
10
Total Applications
across all art units

Statute-Specific Performance

§103
46.7%
+6.7% vs TC avg
§102
23.3%
-16.7% vs TC avg
§112
26.7%
-13.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 0 resolved cases

Office Action

§102 §112
DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). Status of claim(s) to be treated in this office action: Independent: 1, 11, 16, 21 Pending: 1-30 Claim Objections Claim 30 is objected to because of the following informalities: Claim 30 refers to a “third frame” that is coupled to “another surface of the substrate.” A third frame is not recited in the specification, other than the re-statement of the claims and recitation of aspects. A person of ordinary skill in the art (POSITA) before the effective filing date would not be able to determine a third frame and which surface to attach it to. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Dependent Claim 10 recite(s) the limitation "a second frame” in Claim 10, line 1. “A second frame” is recited in Claim 8 (line 3), the claim on which this claim depends. It is unclear whether this is a different “second frame” than the one recited in claim 8, or if it refers back to frame in claim 8. The recitation of “second frame” in Claim 10 is being interpreted as the same instance of “second frame” of Claim 8. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rho (US 12456653 B2). Re: Independent Claim 1, Rho discloses: A package (Rho, semiconductor device; Fig. 1, element 100) comprising: an integrated device (Rho, semiconductor element unit; Fig. 1, element 32); and a substrate (Rho, packaging substrate; Fig. 1, element 20) coupled to the integrated device through at least a plurality of solder interconnects (Rho, element connection unit such as solder ball; Fig. 1, element 51, Col 10, lines 54-57), the substrate comprising: at least one dielectric layer (Rho, upper insulating layer; Fig. 3b, element 253, which can be disposed on first surface, element 213); a frame (Rho, cavity frame; Fig. 10, element 286) at least partially located in the at least one dielectric layer (Rho, Col. 9, lines 9-16); and a plurality of interconnects (Rho, element connection unit; Fig. 1, Col 10, lines 54-57) located at least partially in the at least one dielectric layer. Re: Dependent Claim 2, Rho disclose(s) all the limitations of claim 1 on which this claim depends. Rho further discloses: wherein the substrate (Rho, packaging substrate; Fig. 1, element 20) includes a core layer (Rho, core layer; Fig. 3b, element 22), wherein the frame (Rho, cavity frame; Fig. 9, element 286) is surrounded at least partially by the core layer. Re: Dependent Claim 3, Rho disclose(s) all the limitations of claim 2 on which this claim depends. Rho further discloses: wherein the frame (Rho, cavity frame; Fig. 9, element 286) touches the at least one dielectric layer (Rho, upper insulating layer; Fig. 3b, element 253, which can be disposed on first surface, element 213). Re: Dependent Claim 4, Rho disclose(s) all the limitations of claim 2 on which this claim depends. Rho further discloses: wherein the core layer (Rho, core layer; Fig. 3b, element 22) includes a cavity (Rho, cavity unit; Fig. 3b, element 28), and wherein the frame (Rho, cavity frame; Fig. 10, element 286, is located at least partially in the cavity of the core layer (Rho, core layer; Fig. 3b, element 22). Fig. 10 in Rho shows the frame (element 286) in the cavity (element 28), within the glass substrate (element 21) which is within the core layer (element 22), as shown in Fig. 8. Re: Dependent Claim 5, Rho disclose(s) all the limitations of claim 4 on which this claim depends. Rho further discloses: wherein at least part of the cavity (Rho, cavity unit; Fig. 3b, element 28) of the core layer (Rho, core layer; Fig. 3b, element 22) is occupied by the at least one dielectric layer (Rho, Cavity insulating layer; Fig.4, element 284, Col. 12, lines 29-48). Re: Dependent Claim 6, Rho disclose(s) all the limitations of claim 1 on which this claim depends. Rho further discloses: wherein at least part of the frame (Rho, cavity frame; Fig. 9, element 286) is located along a periphery of the substrate (Rho, packaging substrate; Fig. 1, element 20). Fig. 4a of Rho shows the boundary or edges (periphery) of the substrate (element 20), and Fig. 9 shows at least part of the frame (element 286) located along the boundary/edge of the substrate. Re: Dependent Claim 7, Rho disclose(s) all the limitations of claim 1 on which this claim depends. Rho further discloses: wherein the frame (Rho, cavity frame; Fig. 10, element 286) includes a different material (Rho, cavity frame may be made of substantially the same material as the glass substrate, Col. 6, lines 36-37, the substrate materials are listed on Col.7, lines 14-16) from the plurality of interconnects (Rho, element conversion unit; Fig. 1, element 51). Re: Dependent Claim 8, Rho disclose(s) all the limitations of claim 1 on which this claim depends. Rho further discloses: wherein the frame (Rho, cavity frame; Fig. 10, element 286) is an embedded frame (Rho, Col. 5 and 6, lines 67-5), and wherein the package further comprises a second frame (Rho, supporting unit; Fig. 7, element 285) coupled to a surface (Rho, side wall pattern; Fig. 4, element 283a) of the substrate (Rho, packaging substrate; Fig. 1, element 20). Re: Dependent Claim 9, Rho disclose(s) all the limitations of claim 8 on which this claim depends. Rho further discloses: wherein the surface (Rho, side wall pattern; Fig. 4, element 283a) of the substrate is a landside surface of the substrate (Rho, electrically conductive pattern, Col. 12, lines 29-38). Re: Dependent Claim 10, Rho disclose(s) all the limitations of claim 8 on which this claim depends. Rho further discloses: further comprising a second frame (Rho, supporting unit; Fig. 7, element 285) coupled to another surface of the substrate (Rho, second side plane; Fig. 6, element 281b). Re: Independent Claim 11, Rho discloses: A package comprising (Rho, semiconductor device; Fig. 1, element 100): an integrated device (Rho, semiconductor element unit; Fig. 1, element 32); a substrate (Rho, packaging substrate; Fig. 1, element 20) coupled to the integrated device through at least a plurality of solder interconnects (Rho, element connection unit such as solder ball; Fig. 1, element 51, Col 10, lines 54-57), wherein the integrated device is coupled to a first surface of the substrate (Rho, packaging substrate; Fig. 1, element 20, Rho shows this on the top surface of the packaging substrate, element 20), the substrate comprising: at least one dielectric layer (Rho, upper insulating layer; Fig. 3b, element 253, which can be disposed on first surface, element 213); and a plurality of interconnects (Rho, element connection unit; Fig. 1, Col 10, lines 54-57) located at least partially in the at least one dielectric layer; a second plurality of solder interconnects (Rho, board connection unit, Fig. 1, element 52) coupled to a second surface of the substrate (Rho, Fig. 1 shows this on the bottom surface of the packaging substrate, element 20); and a first frame (Rho, cavity frame; Fig.9, element 286) coupled to the second surface of the substrate. Re: Dependent Claim 12, Rho disclose(s) all the limitations of claim 11 on which this claim depends. Rho further discloses: further comprising a second frame (Rho, supporting unit; Fig. 7b, element 285) coupled to the first surface of the substrate (Rho, Fig. 8 shows that the second frame is coupled to the top surface of the packaging substrate, element 20). Re: Dependent Claim 13, Rho disclose(s) all the limitations of claim 11 on which this claim depends. Rho further discloses: wherein the substrate (Rho, packaging substrate; Fig. 1, element 20) includes a core layer (Rho, core layer; Fig. 3b, element 22). Re: Dependent Claim 14, Rho disclose(s) all the limitations of claim 11 on which this claim depends. Rho further discloses: wherein the substrate (Rho, packaging substrate; Fig. 1, element 20) includes an embedded frame (Rho, cavity frame; Fig. 10, element 286, Col. 5 and 6, lines 67-5) located in the substrate. Re: Dependent Claim 15, Rho disclose(s) all the limitations of claim 14 on which this claim depends. Rho further discloses: wherein the embedded frame (Rho, cavity frame; Fig. 10, element 286, Col. 5 and 6, lines 67-5) touches the at least one dielectric layer (Rho, upper insulating layer; Fig. 3b, element 253, which can be disposed on first surface, element 213). Re: Independent Claim 16, Rho discloses: A substrate (Rho, packaging substrate; Fig. 1, element 20) comprising: at least one dielectric layer (Rho, upper insulating layer; Fig. 3b, element 253, which can be disposed on first surface, element 213); a first frame (Rho, cavity frame; Fig. 10, element 286) at least partially located in the at least one dielectric layer; and a plurality of interconnects (Rho, element connection unit; Fig. 1, Col 9, lines 9-16 and Col 10, lines 54-57) located at least partially in the at least one dielectric layer. Re: Dependent Claim 17, Rho disclose(s) all the limitations of claim 16 on which this claim depends. Rho further discloses: wherein the substrate (Rho, packaging substrate; Fig. 1, element 20) includes a core layer (Rho, core layer; Fig. 3b, element 22), wherein the first frame (Rho, cavity frame; Fig. 9, element 286) is surrounded at least partially by the core layer. Re: Dependent Claim 18, Rho disclose(s) all the limitations of claim 17 on which this claim depends. Rho further discloses: wherein the first frame (Rho, cavity frame; Fig. 9, element 286) touches the at least one dielectric layer (Rho, upper insulating layer; Fig. 3b, element 253, which can be disposed on first surface, element 213). Re: Dependent Claim 19, Rho disclose(s) all the limitations of claim 17 on which this claim depends. Rho further discloses: wherein the core layer (Rho, core layer; Fig. 3b, element 22), includes a cavity (Rho, cavity unit, Fig. 3b, element 28), and wherein the first frame (Rho, cavity frame; Fig. 9, element 286) is located at least partially in the cavity of the core layer. (Fig. 10 of Rho shows the frame (element 286) in the cavity (element 28), within the glass substrate (element 21) which is within the core layer (element 22), as shown in Fig. 8). Re: Dependent Claim 20, Rho disclose(s) all the limitations of claim 19 on which this claim depends. Rho further discloses: wherein at least part of the cavity (Rho, cavity unit, Fig. 3b, element 28) of the core layer (Rho, core layer; Fig. 3b, element 22), is occupied by the at least one dielectric layer (Rho, Cavity insulating layer; Fig.4, element 284, Col. 12, lines 29-48). Re: Independent Claim 21, Rho discloses: A method (Rho, Col. 14, line 1) for fabricating a package, comprising: providing a substrate (Rho, packaging substrate; Fig. 1, element 20) comprising: at least one dielectric layer (Rho, upper insulating layer; Fig. 3b, element 253, which can be disposed on first surface, element 213); a frame (Rho, cavity frame; Fig. 9, element 286) at least partially located in the at least one dielectric layer (Rho, upper insulating layer; Fig. 3b, element 253, which can be disposed on first surface, element 213); and a plurality of interconnects (Rho, element connection unit; Fig. 1, Col 9, lines 9-16 and Col 10, lines 54-57) located at least partially in the at least one dielectric layer; and coupling an integrated device (Rho, semiconductor element unit; Fig. 1, element 32) to the substrate through at least a plurality of solder interconnects. Re: Dependent Claim 22, Rho disclose(s) all the limitations of claim 21 on which this claim depends. Rho further discloses: wherein the substrate (Rho, packaging substrate; Fig. 1, element 20) includes a core layer (Rho, core layer; Fig. 3b, element 22), wherein the frame (Rho, cavity frame; Fig. 9, element 286) is surrounded at least partially by the core layer. Re: Dependent Claim 23, Rho disclose(s) all the limitations of claim 22 on which this claim depends. Rho further discloses: wherein the frame (Rho, cavity frame; Fig. 9, element 286) touches the at least one dielectric layer (Rho, upper insulating layer; Fig. 3b, element 253, which can be disposed on first surface, element 213). Re: Dependent Claim 24, Rho disclose(s) all the limitations of claim 22 on which this claim depends. Rho further discloses: wherein the core layer (Rho, core layer; Fig. 3b, element 22), includes a cavity (Rho, cavity unit, Fig. 3b, element 28), and wherein the frame is located at least partially in the cavity of the core layer. (Fig. 10 of Rho shows the frame (element 286) in the cavity (element 28), within the glass substrate (element 21) which is within the core layer (element 22), as shown in Fig. 8). Re: Dependent Claim 25, Rho disclose(s) all the limitations of claim 24 on which this claim depends. Rho further discloses: wherein at least part of the cavity (Rho, cavity unit, Fig. 3b, element 28) of the core layer (Rho, core layer; Fig. 3b, element 22), is occupied by the at least one dielectric layer (Rho, Cavity insulating layer; Fig.4, element 284, Col. 12, lines 29-48). Re: Dependent Claim 26, Rho disclose(s) all the limitations of claim 21 on which this claim depends. Rho further discloses: wherein at least part of the frame (Rho, cavity frame; Fig. 9, element 286) is located along a periphery of the substrate (Rho, packaging substrate; Fig. 1, element 20). Fig. 4a of Rho shows the boundary or edges (periphery) of the substrate (element 20), and Fig. 9 shows at least part of the frame (element 286) located along the boundary/edge of the substrate). Re: Dependent Claim 27, Rho disclose(s) all the limitations of claim 21 on which this claim depends. Rho further discloses: wherein the frame (Rho, cavity frame; Fig. 10, element 286) includes a different material (Rho, cavity frame may be made of substantially the same material as the glass substrate, Col. 6, lines 36-37, the substrate materials are listed on Col.7, lines 14-16) from the plurality of interconnects (Rho, element conversion unit; Fig. 1, Col 9, lines 9-16 and Col 10, lines 54-57). Re: Dependent Claim 28, Rho disclose(s) all the limitations of claim 21 on which this claim depends. Rho further discloses: wherein the frame (Rho, cavity frame; Fig. 10, element 286) is an embedded frame (Rho, Col. 5 and 6, lines 67-5), and wherein the method further comprises coupling a second frame (Rho, supporting unit; Fig. 7b, element 285) to a surface of the substrate (Rho, Fig. 8, frame is coupled to the surface of the substrate). Re: Dependent Claim 29, Rho disclose(s) all the limitations of claim 28 on which this claim depends. Rho further discloses: wherein the surface (Rho, side wall pattern; Fig. 4, element 283a) of the substrate (Rho, package substrate, Fig. 1, element 20) is a landside surface of the substrate (Rho, electrically conductive pattern, Col. 12, lines 29-38). Re: Dependent Claim 30, Rho disclose(s) all the limitations of claim 28 on which this claim depends. Rho further discloses: further comprising coupling a third frame (Rho, supporting unit; Fig. 6, element 285) to another surface (Rho, Fig. 6, the frame not previously referred to can be considered as the third frame which is attached to another surface (element 281a) of the substrate (Rho, package substrate; Fig.1, element 20). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 7:00 AM - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMARTA KAUR CHOWDHARY/ Examiner, Art Unit 2898 /Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Aug 25, 2023
Application Filed
Jan 14, 2026
Non-Final Rejection — §102, §112 (current)

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month